starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2020-01-10	clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()	Sowjanya Komatineni	1	-2/+1
2019-11-11	clk: tegra: clk-dfll: Add suspend and resume support	Sowjanya Komatineni	1	-0/+56
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	Thomas Gleixner	1	-10/+1
2019-03-14	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	1	-9/+9
2019-02-22	clk: tegra: dfll: Fix debugfs_simple_attr.cocci warnings	YueHaibing	1	-9/+9
2019-02-06	clk: tegra: dfll: round down voltages based on alignment	Joseph Lo	1	-8/+13
2019-02-06	clk: tegra: dfll: support PWM regulator control	Joseph Lo	1	-67/+377
2018-11-29	clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macro	Yangtao Li	1	-11/+1
2018-10-17	clk: tegra: probe deferral error reporting	Marcel Ziswiler	1	-2/+6
2018-06-02	clk: tegra: no need to check return value of debugfs_create functions	Greg Kroah-Hartman	1	-31/+11
2017-11-01	clk: tegra: dfll: Fix drvdata overwriting issue	Nicolin Chen	1	-5/+5
2017-01-30	PM / OPP: Update OPP users to put reference	Viresh Kumar	1	-11/+6
2016-04-28	clk: tegra: dfll: Reference CVB table instead of copying data	Thierry Reding	1	-5/+6
2016-03-03	clk: tegra: Remove CLK_IS_ROOT	Stephen Boyd	1	-1/+0
2015-10-20	Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...	Michael Turquette	1	-57/+57
2015-10-20	clk: tegra: dfll: Monitor code is DEBUG_FS only	Thierry Reding	1	-50/+49
2015-09-17	clk: tegra: dfll: Properly protect OPP list	Thierry Reding	1	-1/+7
2015-09-15	clk: tegra: Unlock top rates for Tegra124 DFLL clock	Mikko Perttunen	1	-7/+8
2015-08-26	clk: tegra: Fix some static checker problems	Stephen Boyd	1	-3/+5
2015-07-16	clk: tegra: Add Tegra124 DFLL clocksource platform driver	Tuomas Tynkkynen	1	-3/+3
2015-07-16	clk: tegra: Add closed loop support for the DFLL	Tuomas Tynkkynen	1	-3/+663
2015-07-16	clk: tegra: Add library for the DFLL clock source (open-loop mode)	Tuomas Tynkkynen	1	-0/+1095