starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2014-02-18	clk: sunxi: Add support for PLL6 on the A31	Maxime Ripard	1	-0/+45
2014-02-18	clk: sunxi: Add USB clock register defintions	Roman Byshko	1	-0/+12
2014-02-18	clk: sunxi: Add support for USB clock-register reset bits	Hans de Goede	1	-0/+71
2014-02-03	clk: sunxi: get divs parent clock name from parent factor clock	Chen-Yu Tsai	1	-1/+2
2014-02-03	clk: sunxi: add names for pll5, pll6 parent clocks to factors_data	Chen-Yu Tsai	1	-9/+18
2014-02-03	clk: sunxi: add clock-output-names dt property support	Chen-Yu Tsai	1	-0/+6
2014-01-28	clk: sunxi: fix overflow when setting up divided factors	Emilio López	1	-1/+1
2013-12-29	clk: sunxi: Allwinner A20 output clock support	Chen-Yu Tsai	1	-0/+57
2013-12-29	clk: sunxi: support better factor DT nodes	Emilio López	1	-0/+9
2013-12-29	clk: sunxi: mod0 support	Emilio López	1	-0/+57
2013-12-29	clk: sunxi: add PLL5 and PLL6 support	Emilio López	1	-0/+230
2013-12-29	clk: sunxi: make factors_clk_setup return the clock it registers	Emilio López	1	-7/+8
2013-12-29	clk: sunxi: add gating support to PLL1	Emilio López	1	-0/+2
2013-12-29	clk: sunxi: clean the magic number of mux parents	Emilio López	1	-2/+3
2013-12-29	clk: sunxi: register factors clocks behind composite	Emilio López	3	-73/+76
2013-12-02	Merge tag 'sunxi-clk-for-3.13' of https://github.com/mripard/linux into clk-n...	Mike Turquette	2	-14/+48
2013-11-10	drivers: clk: sunxi: Fix memory leakage in clk-sunxi.c	Victor N. Ramos Mello	1	-11/+17
2013-11-10	clk: sunxi: protect core clocks from accidental shutdown	Emilio López	1	-0/+28
2013-11-10	clk: sunxi: factors: clear variables before using them	Emilio López	1	-1/+1
2013-11-10	clk: sunxi: factors: fix off-by-one masks	Emilio López	1	-1/+1
2013-09-29	clk: sunxi: declare OF clock provider	Sebastian Hesselbarth	1	-5/+6
2013-08-28	clk: sunxi: Fix incorrect placement of __initconst	Sachin Kamat	1	-30/+30
2013-08-26	clk: sunxi: Add Allwinner A20 gates	Maxime Ripard	1	-0/+15
2013-08-26	clk: sunxi: Add A31 clocks support	Maxime Ripard	1	-0/+124
2013-08-26	clk: sunxi: Allow to specify the divider width from the dividers data	Maxime Ripard	1	-11/+13
2013-08-26	clk: sunxi: Rename the structure to prepare the addition of sun6i	Maxime Ripard	1	-27/+27
2013-08-26	clk: sunxi: fix initialization of basic clocks	Emilio López	1	-8/+3
2013-08-26	clk: sunxi: Add A10s gates	Maxime Ripard	1	-0/+15
2013-08-19	clk: add CLK_SET_RATE_NO_REPARENT flag	James Hogan	1	-1/+2
2013-08-09	clk: sunxi: Fix checking return value of clk_register_[composite\|factors]	Axel Lin	1	-2/+2
2013-05-30	clk: sunxi: "cpu_data" is defined in header files of some architectures	Giacomo A. Catenazzi	1	-2/+2
2013-05-29	clk: sun5i: Add compatibles for Allwinner A13	Maxime Ripard	1	-8/+23
2013-04-12	clk: sunxi: Unify oscillator clock	Emilio López	1	-7/+26
2013-04-05	clk: sunxi: drop an unnecesary kmalloc	Emilio López	1	-1/+1
2013-04-05	clk: sunxi: drop CLK_IGNORE_UNUSED	Emilio López	1	-4/+4
2013-04-05	clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates	Emilio López	1	-0/+88
2013-03-27	clk: sunxi: rename compatible strings	Emilio López	1	-8/+8
2013-03-27	clk: arm: sunxi: Add a new clock driver for sunxi SOCs	Emilio López	4	-0/+574