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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
sunxi
Age
Commit message (
Expand
)
Author
Files
Lines
2014-07-29
clk: sunxi: staticize structures and arrays
Emilio López
4
-5
/
+5
2014-07-29
clk: sunxi: add __iomem markings to MMIO pointers
Emilio López
2
-6
/
+6
2014-07-26
Merge tag 'sunxi-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kerne...
Mike Turquette
6
-43
/
+227
2014-07-15
clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 support
Chen-Yu Tsai
1
-0
/
+5
2014-07-15
clk: sunxi: sun6i-apb0-gates: use bitmaps for valid gate indices
Chen-Yu Tsai
1
-36
/
+39
2014-07-07
clk: sunxi: Fix gate indexing for sun6i-a31-apb0-gates
Chen-Yu Tsai
1
-1
/
+5
2014-07-07
clk: sunxi: Add A23 APB0 divider clock support
Chen-Yu Tsai
2
-1
/
+71
2014-07-04
clk: sunxi: Add A23 clocks support
Chen-Yu Tsai
1
-0
/
+101
2014-07-04
clk: sunxi: Add support for table-based divider clocks
Chen-Yu Tsai
1
-4
/
+5
2014-07-04
clk: sunxi: Support factor clocks with N factor starting not from 0
Chen-Yu Tsai
2
-1
/
+2
2014-07-04
clk: sunxi: move "ahb_sdram" to protected clock list
Chen-Yu Tsai
1
-5
/
+3
2014-07-04
clk: sunxi: register clock gates with clkdev
Chen-Yu Tsai
1
-0
/
+1
2014-07-02
clk: sunxi: fix devm_ioremap_resource error detection code
Himangi Saraogi
1
-1
/
+1
2014-06-11
clk: sunxi: add PRCM (Power/Reset/Clock Management) clks support
Boris BREZILLON
4
-0
/
+411
2014-06-11
clk: sun6i: Protect SDRAM gating bit
Maxime Ripard
1
-0
/
+1
2014-06-11
clk: sun6i: Protect CPU clock
Maxime Ripard
1
-0
/
+1
2014-06-11
clk: sunxi: Rework clock protection code
Maxime Ripard
1
-28
/
+44
2014-06-11
clk: sunxi: Move the GMAC clock to a file of its own
Maxime Ripard
3
-99
/
+121
2014-06-11
clk: sunxi: Move the 24M oscillator to a file of its own
Maxime Ripard
3
-57
/
+74
2014-06-11
clk: sunxi: Remove calls to clk_put
Maxime Ripard
1
-6
/
+2
2014-06-11
clk: sunxi: Implement A31 USB clock
Maxime Ripard
1
-0
/
+6
2014-06-08
Merge tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/...
Linus Torvalds
2
-0
/
+73
2014-05-20
clk: sunxi: fix function type for CLK_OF_DECLARE
Rob Herring
1
-1
/
+1
2014-05-20
clk: sunxi: avoid double DT matching
Rob Herring
1
-2
/
+1
2014-05-15
clk: sunxi: Fixup clk_sunxi_mmc_phase_control to take a clk rather then a hw_clk
Hans de Goede
1
-1
/
+2
2014-05-06
clk: sunxi: Implement MMC phase control
Emilio López
1
-0
/
+36
2014-05-06
clk: sunxi: factors: automatic reparenting support
Emilio López
1
-0
/
+36
2014-03-19
clk: sunxi: fix thinko in comment
Emilio López
1
-1
/
+1
2014-03-19
clk: sunxi: fix some calculations
Emilio López
1
-3
/
+3
2014-03-19
clk: sunxi: fix A20 PLL4 calculation
Emilio López
1
-0
/
+7
2014-02-18
clk: sunxi: Add new clock compatibles
Maxime Ripard
1
-15
/
+15
2014-02-18
clk: sunxi: Add Allwinner A20/A31 GMAC clock unit
Chen-Yu Tsai
1
-0
/
+96
2014-02-18
clk: sunxi: Add support for PLL6 on the A31
Maxime Ripard
1
-0
/
+45
2014-02-18
clk: sunxi: Add USB clock register defintions
Roman Byshko
1
-0
/
+12
2014-02-18
clk: sunxi: Add support for USB clock-register reset bits
Hans de Goede
1
-0
/
+71
2014-02-03
clk: sunxi: get divs parent clock name from parent factor clock
Chen-Yu Tsai
1
-1
/
+2
2014-02-03
clk: sunxi: add names for pll5, pll6 parent clocks to factors_data
Chen-Yu Tsai
1
-9
/
+18
2014-02-03
clk: sunxi: add clock-output-names dt property support
Chen-Yu Tsai
1
-0
/
+6
2014-01-28
clk: sunxi: fix overflow when setting up divided factors
Emilio López
1
-1
/
+1
2013-12-29
clk: sunxi: Allwinner A20 output clock support
Chen-Yu Tsai
1
-0
/
+57
2013-12-29
clk: sunxi: support better factor DT nodes
Emilio López
1
-0
/
+9
2013-12-29
clk: sunxi: mod0 support
Emilio López
1
-0
/
+57
2013-12-29
clk: sunxi: add PLL5 and PLL6 support
Emilio López
1
-0
/
+230
2013-12-29
clk: sunxi: make factors_clk_setup return the clock it registers
Emilio López
1
-7
/
+8
2013-12-29
clk: sunxi: add gating support to PLL1
Emilio López
1
-0
/
+2
2013-12-29
clk: sunxi: clean the magic number of mux parents
Emilio López
1
-2
/
+3
2013-12-29
clk: sunxi: register factors clocks behind composite
Emilio López
3
-73
/
+76
2013-12-02
Merge tag 'sunxi-clk-for-3.13' of https://github.com/mripard/linux into clk-n...
Mike Turquette
2
-14
/
+48
2013-11-10
drivers: clk: sunxi: Fix memory leakage in clk-sunxi.c
Victor N. Ramos Mello
1
-11
/
+17
2013-11-10
clk: sunxi: protect core clocks from accidental shutdown
Emilio López
1
-0
/
+28
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