| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 | Thomas Gleixner | 28 | -252/+28 |
| 2019-06-05 | clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register | Ondrej Jirman | 1 | -1/+1 |
| 2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 | Thomas Gleixner | 15 | -150/+15 |
| 2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 | Thomas Gleixner | 13 | -65/+13 |
| 2019-05-21 | treewide: Add SPDX license identifier - Makefile/Kconfig | Thomas Gleixner | 1 | -0/+1 |
| 2019-05-15 | clk: Remove io.h from clk-provider.h | Stephen Boyd | 26 | -0/+26 |
| 2019-05-07 | Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and... | Stephen Boyd | 2 | -3/+3 |
| 2019-05-07 | Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' a... | Stephen Boyd | 6 | -13/+23 |
| 2019-05-01 | clk: sunxi-ng: Use the correct style for SPDX License Identifier | Nishad Kamdar | 2 | -3/+3 |
| 2019-04-10 | clk: sunxi-ng: sun5i: Export the MBUS clock | Maxime Ripard | 1 | -4/+0 |
| 2019-04-09 | clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk | Chen-Yu Tsai | 1 | -2/+3 |
| 2019-04-04 | clk: sunxi-ng: nkmp: Explain why zero width check is needed | Jernej Skrabec | 1 | -0/+6 |
| 2019-04-04 | clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate | Jernej Skrabec | 1 | -3/+3 |
| 2019-04-03 | clk: sunxi-ng: h6: Preset hdmi-cec clock parent | Jernej Skrabec | 1 | -0/+11 |
| 2019-04-03 | clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0) | Jernej Skrabec | 1 | -5/+13 |
| 2019-03-18 | clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset | Icenowy Zheng | 1 | -1/+1 |
| 2019-03-18 | clk: sunxi-ng: Allow DE clock to set parent rate | Jernej Skrabec | 3 | -3/+5 |
| 2019-03-08 | Merge branches 'clk-optional', 'clk-devm-clkdev-register', 'clk-allwinner', '... | Stephen Boyd | 1 | -1/+1 |
| 2019-01-28 | clk: sunxi: A31: Fix wrong AHB gate number | Andre Przywara | 1 | -2/+2 |
| 2019-01-25 | clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating it | Chen-Yu Tsai | 1 | -1/+1 |
| 2019-01-22 | clk: sunxi-ng: v3s: Fix TCON reset de-assert bit | Paul Kocialkowski | 1 | -1/+1 |
| 2018-12-10 | clk: sunxi-ng: a64: Allow parent change for VE clock | Jernej Skrabec | 1 | -1/+1 |
| 2018-12-05 | clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks | Chen-Yu Tsai | 1 | -3/+3 |
| 2018-12-05 | clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL | Chen-Yu Tsai | 1 | -13/+24 |
| 2018-12-04 | clk: sunxi-ng: h3: Allow parent change for ve clock | Jernej Skrabec | 1 | -1/+1 |
| 2018-12-04 | clk: sunxi-ng: add support for suniv F1C100s SoC | Mesih Kilinc | 4 | -0/+581 |
| 2018-12-03 | clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent | Chen-Yu Tsai | 1 | -1/+1 |
| 2018-11-30 | clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output | Chen-Yu Tsai | 1 | -0/+11 |
| 2018-11-23 | clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL | Chen-Yu Tsai | 1 | -13/+24 |
| 2018-11-13 | clk: sunxi-ng: a64: Fix gate bit of DSI DPHY | Jagan Teki | 1 | -1/+1 |
| 2018-11-13 | clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I | Jagan Teki | 1 | -0/+1 |
| 2018-11-05 | clk: sunxi-ng: Add support for H6 DE3 clocks | Jernej Skrabec | 2 | -4/+71 |
| 2018-11-05 | clk: sunxi-ng: h6: Set video PLLs limits | Jernej Skrabec | 1 | -0/+4 |
| 2018-11-05 | clk: sunxi-ng: Use u64 for calculation of NM rate | Jernej Skrabec | 1 | -3/+15 |
| 2018-11-05 | clk: sunxi-ng: Adjust MP clock parent rate when allowed | Jernej Skrabec | 1 | -2/+62 |
| 2018-11-05 | clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width | Jagan Teki | 1 | -3/+3 |
| 2018-11-05 | clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock | Icenowy Zheng | 1 | -1/+6 |
| 2018-10-31 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 10 | -86/+143 |
| 2018-09-07 | clk: sunxi-ng: sun4i: Set VCO and PLL bias current to lowest setting | Chen-Yu Tsai | 1 | -1/+9 |
| 2018-09-05 | dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro | Jagan Teki | 1 | -1/+3 |
| 2018-09-05 | clk: sunxi-ng: a64: Add max. rate constraint to video PLLs | Icenowy Zheng | 1 | -24/+26 |
| 2018-09-05 | clk: sunxi-ng: a64: Add minimal rate for video PLLs | Jagan Teki | 1 | -22/+24 |
| 2018-09-05 | clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks | Icenowy Zheng | 1 | -20/+23 |
| 2018-08-27 | clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs | Jernej Skrabec | 1 | -0/+2 |
| 2018-08-27 | clk: sunxi-ng: nkmp: Add constraint for maximum rate | Jernej Skrabec | 2 | -0/+8 |
| 2018-08-27 | clk: sunxi-ng: r40: Add max. rate constraint to video PLLs | Jernej Skrabec | 1 | -26/+26 |
| 2018-08-27 | clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video | Jernej Skrabec | 1 | -12/+13 |
| 2018-08-27 | clk: sunxi-ng: Add maximum rate constraint to NM PLLs | Jernej Skrabec | 2 | -0/+37 |
| 2018-08-27 | clk: sunxi-ng: h6: fix PWM gate/reset offset | Rongyi Chen | 1 | -1/+1 |
| 2018-08-27 | clk: sunxi-ng: h6: fix bus clocks' divider position | Icenowy Zheng | 1 | -4/+4 |
