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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
sunxi-ng
Age
Commit message (
Expand
)
Author
Files
Lines
2020-02-12
clk: sunxi-ng: sun8i-de2: Sort structures
Jernej Skrabec
1
-10
/
+10
2020-02-12
clk: sunxi-ng: sun8i-de2: Add R40 specific quirks
Jernej Skrabec
1
-0
/
+14
2020-02-12
clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T
Jernej Skrabec
1
-1
/
+11
2020-02-12
clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets
Jernej Skrabec
1
-7
/
+16
2020-02-12
clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core
Jernej Skrabec
1
-56
/
+1
2020-02-12
clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64
Jernej Skrabec
1
-3
/
+42
2020-02-12
clk: sunxi-ng: sun8i-de2: Split out H5 definitions
Jernej Skrabec
1
-1
/
+17
2020-02-11
clk: sunxi-ng: a64: Export MBUS clock
Jernej Skrabec
1
-4
/
+0
2020-02-04
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
5
-8
/
+33
2020-01-04
clk: sunxi: a23/a33: Export the MIPI PLL
Maxime Ripard
1
-1
/
+3
2020-01-04
clk: sunxi: a31: Export the MIPI PLL
Maxime Ripard
1
-1
/
+3
2020-01-04
clk: sunxi-ng: a64: export CLK_CPUX clock for DVFS
Vasily Khoruzhick
1
-1
/
+0
2020-01-04
clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
Icenowy Zheng
1
-1
/
+27
2020-01-03
clk: sunxi-ng: r40: Export MBUS clock
Chen-Yu Tsai
1
-4
/
+0
2020-01-02
clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order
Samuel Holland
1
-2
/
+2
2020-01-02
clk: sunxi-ng: h6-r: Simplify R_APB1 clock definition
Samuel Holland
1
-11
/
+1
2020-01-02
clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock
Samuel Holland
1
-18
/
+3
2019-12-19
clk: sunxi-ng: r40: Allow setting parent rate for external clock outputs
Chen-Yu Tsai
1
-2
/
+4
2019-12-09
clk: sunxi-ng: v3s: Fix incorrect number of hw_clks.
Yunhao Tian
2
-4
/
+2
2019-12-02
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
2
-11
/
+16
2019-11-05
clk: sunxi-ng: h3: Export MBUS clock
Jernej Skrabec
1
-4
/
+0
2019-10-29
clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18
Colin Ian King
1
-1
/
+1
2019-10-02
clk: sunxi-ng: h6: Allow GPU to change parent rate
Jernej Skrabec
1
-1
/
+1
2019-09-30
clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL
Jernej Skrabec
1
-6
/
+15
2019-09-20
Merge branches 'clk-init-destroy', 'clk-doc', 'clk-imx' and 'clk-allwinner' i...
Stephen Boyd
4
-14
/
+255
2019-08-21
clk: sunxi-ng: h6: Allow I2S to change parent rate
Jernej Skrabec
1
-4
/
+4
2019-08-16
clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered
Stephen Boyd
1
-2
/
+3
2019-08-12
clk: sunxi-ng: v3s: add Allwinner V3 support
Icenowy Zheng
2
-3
/
+227
2019-08-12
clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
Icenowy Zheng
1
-0
/
+3
2019-07-22
clk: sunxi-ng: v3s: add the missing PLL_DDR1
Icenowy Zheng
2
-6
/
+19
2019-07-17
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
16
-221
/
+397
2019-06-25
Merge tag 'sunxi-ng-parent-rewrite-part-1-take-2' of https://git.kernel.org/p...
Stephen Boyd
16
-220
/
+396
2019-06-22
clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
Chen-Yu Tsai
1
-14
/
+23
2019-06-22
clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
Chen-Yu Tsai
1
-12
/
+20
2019-06-22
clk: sunxi-ng: gate: Add macros for referencing local clock parents
Chen-Yu Tsai
1
-0
/
+53
2019-06-22
clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-1
/
+1
2019-06-22
clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-25
/
+44
2019-06-22
clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-15
/
+26
2019-06-22
clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-10
/
+19
2019-06-18
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-1
/
+1
2019-06-18
clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-10
/
+19
2019-06-18
clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-17
/
+29
2019-06-18
clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-10
/
+19
2019-06-18
clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-12
/
+22
2019-06-18
clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-12
/
+22
2019-06-18
clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-14
/
+25
2019-06-18
clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-12
/
+22
2019-06-18
clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-14
/
+25
2019-06-18
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
Chen-Yu Tsai
1
-40
/
+25
2019-06-18
clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
Chen-Yu Tsai
1
-1
/
+1
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