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path: root/drivers/clk/st/clkgen-pll.c
AgeCommit message (Expand)AuthorFilesLines
2021-06-28clk: st: clkgen-pll: embed soc clock outputs within compatible dataAlain Volmat1-14/+106
2021-06-28clk: st: clkgen-pll: remove unused variable of struct clkgen_pllAlain Volmat1-1/+0
2021-02-11clk: st: clkgen-pll: Demote unpopulated kernel-doc headerLee Jones1-2/+1
2019-09-06clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0'YueHaibing1-13/+0
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner1-6/+1
2018-12-11clk: st: Remove usage of CLK_IS_BASICStephen Boyd1-1/+1
2018-06-13treewide: kzalloc() -> kcalloc()Kees Cook1-1/+1
2016-09-17drivers: clk: st: Simplify clock binding of STiH4xx platformsGabriel Fernandez1-34/+29
2016-09-17drivers: clk: st: Remove stih415-416 clock supportGabriel Fernandez1-419/+0
2016-06-30clk: st: clkgen-pll: Detect critical clocksLee Jones1-10/+17
2015-10-09drivers: clk: st: Correct the pll-type for A9 for stih418Gabriel Fernandez1-0/+194
2015-10-09drivers: clk: st: PLL rate change implementation for DVFSGabriel Fernandez1-10/+211
2015-10-09drivers: clk: st: Support for enable/disable in Clockgen PLLsGabriel Fernandez1-1/+59
2015-09-17drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_xGabriel Fernandez1-6/+6
2015-08-25clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd1-4/+4
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd1-0/+1
2015-07-20clk: st: Include clk.hStephen Boyd1-0/+1
2015-07-06drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocksPankaj Dev1-1/+1
2015-05-15clk: st: Silence sparse warningsStephen Boyd1-5/+5
2015-04-01clk: constify of_device_id arrayFabian Frederick1-2/+2
2014-07-29clk: st: STiH407: Support for clockgenA9Gabriel FERNANDEZ1-0/+16
2014-07-29clk: st: STiH407: Support for clockgenC0Gabriel FERNANDEZ1-0/+32
2014-07-29clk: st: STiH407: Support for clockgenA0Gabriel FERNANDEZ1-0/+16
2014-07-29clk: st: use static const for clkgen_pll_data tablesGabriel FERNANDEZ1-16/+14
2014-05-28clk: st: Terminate of match tableStephen Boyd1-0/+1
2014-05-24clk: st: Fix memory leakValentin Ilie1-1/+3
2014-03-26clk: st: Support for ClockGenA9/DDR/GPUGabriel FERNANDEZ1-0/+139
2014-03-26clk: st: Support for PLLs inside ClockGenA(s)Gabriel FERNANDEZ1-0/+559
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