starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2012-07-18	Clk: SPEAr1340: Update sys clock parent array	Vipul Kumar Samar	1	-2/+2
2012-07-18	clk: SPEAr1340: Fix clk enable register for uart1 and i2c1.	Vipul Kumar Samar	1	-2/+2
2012-07-18	Clk:spear6xx:Fix: Rename clk ids within predefined limit	Vipul Kumar Samar	1	-62/+60
2012-07-18	Clk:spear3xx:Fix: Rename clk ids within predefined limit	Vipul Kumar Samar	1	-94/+86
2012-07-18	clk:spear1310:Fix: Rename clk ids within predefined limit	Vipul Kumar Samar	1	-157/+155
2012-07-18	clk:spear1340:Fix: Rename clk ids within predefined limit	Vipul Kumar Samar	1	-138/+135
2012-06-26	clk: SPEAr600: Fix ethernet clock name for DT based probing	Stefan Roese	1	-1/+1
2012-06-21	Viresh has moved	Viresh Kumar	10	-10/+10
2012-05-14	SPEAr13xx: Add common clock framework support	Viresh Kumar	3	-0/+2072
2012-05-12	SPEAr: Switch to common clock framework	Viresh Kumar	3	-0/+957
2012-05-12	SPEAr: clk: Add General Purpose Timer Synthesizer clock	Viresh Kumar	3	-1/+172
2012-05-12	SPEAr: clk: Add Fractional Synthesizer clock	Viresh Kumar	3	-1/+182
2012-05-12	SPEAr: clk: Add Auxiliary Synthesizer clock	Viresh Kumar	3	-1/+242
2012-05-12	SPEAr: clk: Add VCO-PLL Synthesizer clock	Viresh Kumar	4	-0/+462