index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
clk
/
spear
Age
Commit message (
Expand
)
Author
Files
Lines
2016-03-03
clk: spear: Remove CLK_IS_ROOT
Stephen Boyd
4
-32
/
+19
2015-09-01
Merge tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/gi...
Linus Torvalds
4
-4
/
+1
2015-08-25
clk: spear: Convert to clk_hw based provider APIs
Stephen Boyd
1
-1
/
+1
2015-07-20
clk: spear: Remove clk.h include
Stephen Boyd
3
-3
/
+0
2015-07-18
Update Viresh Kumar's email address
Viresh Kumar
10
-10
/
+10
2014-07-13
Merge branch 'clk-fixes' into clk-next
Mike Turquette
1
-5
/
+11
2014-07-13
clk: spear3xx: Set proper clock parent of uart1/2
Thomas Gleixner
1
-4
/
+10
2014-07-13
clk: spear3xx: Use proper control register offset
Thomas Gleixner
1
-1
/
+1
2014-07-11
ARM: SPEAr13xx: Fix pcie clock name
Pratyush Anand
2
-4
/
+4
2013-12-19
clk: SPEAr: Staticize clk_frac_ops
Sachin Kamat
1
-1
/
+1
2013-08-19
clk: add CLK_SET_RATE_NO_REPARENT flag
James Hogan
4
-167
/
+201
2013-06-12
clk: spear: fix build error for spear3xx
Arnd Bergmann
1
-1
/
+1
2013-05-02
Merge tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/ker...
Linus Torvalds
4
-106
/
+112
2013-03-22
clk:SPEAr1340: Correct parent clock configuration
Vipul Kumar Samar
1
-9
/
+9
2013-03-12
ARM: spear: make clock driver independent of headers
Arnd Bergmann
4
-106
/
+112
2012-12-15
Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Linus Torvalds
1
-0
/
+1
2012-11-26
ARM: SPEAr1310: Move 1310 specific misc register into machine specific files
Vipul Kumar Samar
1
-0
/
+1
2012-11-21
CLK: SPEAr: Remove unused dummy apb_pclk
Vipul Kumar Samar
4
-12
/
+0
2012-11-21
CLK: SPEAr: Correct index scanning done for clock synths
Deepak Sikri
1
-0
/
+3
2012-11-21
CLK: SPEAr: Update clock rate table
Deepak Sikri
4
-21
/
+89
2012-11-21
CLK: SPEAr: Add missing clocks
Vipul Kumar Samar
3
-0
/
+16
2012-11-21
CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks
Vipul Kumar Samar
5
-114
/
+133
2012-11-21
CLK: SPEAr13xx: fix parent names of multiple clocks
Shiraz Hashim
2
-4
/
+4
2012-11-21
CLK: SPEAr13xx: Fix mux clock names
Shiraz Hashim
2
-12
/
+12
2012-11-21
CLK: SPEAr: Fix dev_id & con_id for multiple clocks
Rajeev Kumar
4
-41
/
+49
2012-11-15
clk: spear: Add stub functions for spear3[0|1|2]0_clk_init()
Axel Lin
1
-0
/
+6
2012-10-29
clk: SPEAr: Vco-pll: Fix compilation warning
Viresh Kumar
1
-1
/
+1
2012-07-18
Clk: SPEAr1340: Update sys clock parent array
Vipul Kumar Samar
1
-2
/
+2
2012-07-18
clk: SPEAr1340: Fix clk enable register for uart1 and i2c1.
Vipul Kumar Samar
1
-2
/
+2
2012-07-18
Clk:spear6xx:Fix: Rename clk ids within predefined limit
Vipul Kumar Samar
1
-62
/
+60
2012-07-18
Clk:spear3xx:Fix: Rename clk ids within predefined limit
Vipul Kumar Samar
1
-94
/
+86
2012-07-18
clk:spear1310:Fix: Rename clk ids within predefined limit
Vipul Kumar Samar
1
-157
/
+155
2012-07-18
clk:spear1340:Fix: Rename clk ids within predefined limit
Vipul Kumar Samar
1
-138
/
+135
2012-06-26
clk: SPEAr600: Fix ethernet clock name for DT based probing
Stefan Roese
1
-1
/
+1
2012-06-21
Viresh has moved
Viresh Kumar
10
-10
/
+10
2012-05-14
SPEAr13xx: Add common clock framework support
Viresh Kumar
3
-0
/
+2072
2012-05-12
SPEAr: Switch to common clock framework
Viresh Kumar
3
-0
/
+957
2012-05-12
SPEAr: clk: Add General Purpose Timer Synthesizer clock
Viresh Kumar
3
-1
/
+172
2012-05-12
SPEAr: clk: Add Fractional Synthesizer clock
Viresh Kumar
3
-1
/
+182
2012-05-12
SPEAr: clk: Add Auxiliary Synthesizer clock
Viresh Kumar
3
-1
/
+242
2012-05-12
SPEAr: clk: Add VCO-PLL Synthesizer clock
Viresh Kumar
4
-0
/
+462