Age | Commit message (Expand) | Author | Files | Lines |
2012-12-15 | Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc | Linus Torvalds | 1 | -0/+1 |
2012-11-26 | ARM: SPEAr1310: Move 1310 specific misc register into machine specific files | Vipul Kumar Samar | 1 | -0/+1 |
2012-11-21 | CLK: SPEAr: Remove unused dummy apb_pclk | Vipul Kumar Samar | 4 | -12/+0 |
2012-11-21 | CLK: SPEAr: Correct index scanning done for clock synths | Deepak Sikri | 1 | -0/+3 |
2012-11-21 | CLK: SPEAr: Update clock rate table | Deepak Sikri | 4 | -21/+89 |
2012-11-21 | CLK: SPEAr: Add missing clocks | Vipul Kumar Samar | 3 | -0/+16 |
2012-11-21 | CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks | Vipul Kumar Samar | 5 | -114/+133 |
2012-11-21 | CLK: SPEAr13xx: fix parent names of multiple clocks | Shiraz Hashim | 2 | -4/+4 |
2012-11-21 | CLK: SPEAr13xx: Fix mux clock names | Shiraz Hashim | 2 | -12/+12 |
2012-11-21 | CLK: SPEAr: Fix dev_id & con_id for multiple clocks | Rajeev Kumar | 4 | -41/+49 |
2012-11-15 | clk: spear: Add stub functions for spear3[0|1|2]0_clk_init() | Axel Lin | 1 | -0/+6 |
2012-10-29 | clk: SPEAr: Vco-pll: Fix compilation warning | Viresh Kumar | 1 | -1/+1 |
2012-07-18 | Clk: SPEAr1340: Update sys clock parent array | Vipul Kumar Samar | 1 | -2/+2 |
2012-07-18 | clk: SPEAr1340: Fix clk enable register for uart1 and i2c1. | Vipul Kumar Samar | 1 | -2/+2 |
2012-07-18 | Clk:spear6xx:Fix: Rename clk ids within predefined limit | Vipul Kumar Samar | 1 | -62/+60 |
2012-07-18 | Clk:spear3xx:Fix: Rename clk ids within predefined limit | Vipul Kumar Samar | 1 | -94/+86 |
2012-07-18 | clk:spear1310:Fix: Rename clk ids within predefined limit | Vipul Kumar Samar | 1 | -157/+155 |
2012-07-18 | clk:spear1340:Fix: Rename clk ids within predefined limit | Vipul Kumar Samar | 1 | -138/+135 |
2012-06-26 | clk: SPEAr600: Fix ethernet clock name for DT based probing | Stefan Roese | 1 | -1/+1 |
2012-06-21 | Viresh has moved | Viresh Kumar | 10 | -10/+10 |
2012-05-14 | SPEAr13xx: Add common clock framework support | Viresh Kumar | 3 | -0/+2072 |
2012-05-12 | SPEAr: Switch to common clock framework | Viresh Kumar | 3 | -0/+957 |
2012-05-12 | SPEAr: clk: Add General Purpose Timer Synthesizer clock | Viresh Kumar | 3 | -1/+172 |
2012-05-12 | SPEAr: clk: Add Fractional Synthesizer clock | Viresh Kumar | 3 | -1/+182 |
2012-05-12 | SPEAr: clk: Add Auxiliary Synthesizer clock | Viresh Kumar | 3 | -1/+242 |
2012-05-12 | SPEAr: clk: Add VCO-PLL Synthesizer clock | Viresh Kumar | 4 | -0/+462 |