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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
spear
/
spear1310_clock.c
Age
Commit message (
Expand
)
Author
Files
Lines
2017-11-02
CLK: SPEAr: make aux_clk_masks structures const
Bhumika Goyal
1
-1
/
+1
2016-03-03
clk: spear: Remove CLK_IS_ROOT
Stephen Boyd
1
-13
/
+8
2015-09-01
Merge tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/gi...
Linus Torvalds
1
-1
/
+0
2015-07-20
clk: spear: Remove clk.h include
Stephen Boyd
1
-1
/
+0
2015-07-18
Update Viresh Kumar's email address
Viresh Kumar
1
-1
/
+1
2014-07-11
ARM: SPEAr13xx: Fix pcie clock name
Pratyush Anand
1
-3
/
+3
2013-08-19
clk: add CLK_SET_RATE_NO_REPARENT flag
James Hogan
1
-86
/
+93
2013-03-12
ARM: spear: make clock driver independent of headers
Arnd Bergmann
1
-33
/
+31
2012-12-15
Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Linus Torvalds
1
-0
/
+1
2012-11-26
ARM: SPEAr1310: Move 1310 specific misc register into machine specific files
Vipul Kumar Samar
1
-0
/
+1
2012-11-21
CLK: SPEAr: Remove unused dummy apb_pclk
Vipul Kumar Samar
1
-3
/
+0
2012-11-21
CLK: SPEAr: Update clock rate table
Deepak Sikri
1
-0
/
+14
2012-11-21
CLK: SPEAr: Add missing clocks
Vipul Kumar Samar
1
-0
/
+4
2012-11-21
CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks
Vipul Kumar Samar
1
-24
/
+25
2012-11-21
CLK: SPEAr13xx: fix parent names of multiple clocks
Shiraz Hashim
1
-1
/
+1
2012-11-21
CLK: SPEAr13xx: Fix mux clock names
Shiraz Hashim
1
-2
/
+2
2012-11-21
CLK: SPEAr: Fix dev_id & con_id for multiple clocks
Rajeev Kumar
1
-14
/
+16
2012-07-18
clk:spear1310:Fix: Rename clk ids within predefined limit
Vipul Kumar Samar
1
-157
/
+155
2012-06-21
Viresh has moved
Viresh Kumar
1
-1
/
+1
2012-05-14
SPEAr13xx: Add common clock framework support
Viresh Kumar
1
-0
/
+1106