starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2020-05-27	clk: socfpga: agilex: add clock driver for the Agilex platform	Dinh Nguyen	4	-0/+526
2020-05-27	clk: socfpga: add const to _ops data structures	Dinh Nguyen	3	-4/+4
2020-05-27	clk: socfpga: remove clk_ops enable/disable methods	Dinh Nguyen	3	-6/+0
2020-05-27	clk: socfpga: stratix10: use new parent data scheme	Dinh Nguyen	5	-41/+146
2020-02-13	clk: socfpga: stratix10: simplify parameter passing	Dinh Nguyen	5	-92/+57
2020-02-13	clk: stratix10: use do_div() for 64-bit calculation	Dinh Nguyen	1	-1/+3
2019-09-21	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	2	-14/+17
2019-08-16	clk: socfpga: deindent code to proper indentation	Stephen Boyd	1	-2/+2
2019-08-16	clk: socfpga: Don't reference clk_init_data after registration	Stephen Boyd	2	-13/+16
2019-08-14	clk: socfpga: stratix10: fix rate caclulationg for cnt_clks	Dinh Nguyen	1	-1/+1
2019-07-17	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	1	-1/+5
2019-06-28	Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...	Linus Torvalds	1	-2/+2
2019-06-26	clk: socfpga: stratix10: fix divider entry for the emac clocks	Dinh Nguyen	1	-2/+2
2019-06-26	clk: socfpga: stratix10: add additional clocks needed for the NAND IP	Dinh Nguyen	1	-1/+5
2019-06-25	clk: socfpga: stratix10: fix divider entry for the emac clocks	Dinh Nguyen	1	-2/+2
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	Thomas Gleixner	1	-10/+1
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	Thomas Gleixner	3	-36/+3
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	Thomas Gleixner	3	-33/+3
2019-05-21	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13	Thomas Gleixner	1	-13/+1
2019-05-15	clk: Remove io.h from clk-provider.h	Stephen Boyd	3	-0/+3
2019-03-08	Merge branches 'clk-of-refcount', 'clk-mmio-fixed-clock', 'clk-remove-clps', ...	Stephen Boyd	3	-9/+15
2019-01-24	clk: socfpga: Don't have get_parent for single parent ops	Stephen Boyd	1	-9/+13
2019-01-15	clk: socfpga: stratix10: fix naming convention for the fixed-clocks	Dinh Nguyen	1	-10/+10
2019-01-12	clk: socfpga: stratix10: fix rate calculation for pll clocks	Dinh Nguyen	1	-1/+1
2018-12-28	clk: socfpga: fix refcount leak	Yangtao Li	2	-0/+2
2018-07-06	clk: socfpga: stratix10: fix the sdmmc_free_clk mux	Dinh Nguyen	1	-1/+1
2018-07-06	clk: socfpga: stratix10: fix the parents of mpu_free_clk	Dinh Nguyen	1	-1/+6
2018-05-16	clk: socfpga: stratix10: suppress unbinding platform's clock driver	Dinh Nguyen	1	-0/+1
2018-05-16	clk: socfpga: stratix10: use platform driver APIs	Dinh Nguyen	1	-22/+17
2018-04-06	clk: socfpga: stratix10: add clock driver for Stratix10 platform	Dinh Nguyen	7	-5/+853
2017-11-02	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	Greg Kroah-Hartman	1	-0/+1
2017-06-20	clk: socfpga: Fix the smplsel on Arria10 and Stratix10	Dinh Nguyen	2	-1/+4
2016-02-23	clk: socfpga: allow for multiple parents on Arria10 periph clocks	Dinh Nguyen	2	-9/+4
2016-02-09	clk: socfpga: fix __init annotation	Arnd Bergmann	1	-1/+1
2015-08-25	clk: socfpga: Add a second parent option for the dbg_base_clk	Dinh Nguyen	2	-4/+15
2015-07-28	clk: socfpga: switch to GENMASK()	Andy Shevchenko	5	-5/+4
2015-07-20	clk: socfpga: Remove clk.h and clkdev.h includes	Stephen Boyd	7	-7/+6
2015-06-10	clk: socfpga: remove a stray tab	Dan Carpenter	1	-1/+1
2015-06-06	clk: socfpga: make use of of_clk_parent_fill helper function	Dinh Nguyen	2	-11/+2
2015-05-22	clk: socfpga: add a clock driver for the Arria 10 platform	Dinh Nguyen	6	-1/+469
2015-05-22	clk: socfpga: update clk.h so for Arria10 platform to use	Dinh Nguyen	2	-5/+5
2015-05-15	clk: socfpga: Silence sparse warning	Stephen Boyd	1	-1/+1
2015-05-15	clk: socfpga: Silence sparse warning	Stephen Boyd	1	-1/+1
2014-05-13	Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-...	Mike Turquette	3	-4/+23
2014-05-12	clk: socfpga: add divider registers to the main pll outputs	Dinh Nguyen	3	-4/+23
2014-04-30	clk: socfpga: fix clock driver for 3.15	Dinh Nguyen	2	-20/+10
2014-03-19	clk: socfpga: Fix section mismatch warning	Dinh Nguyen	1	-1/+1
2014-02-27	clk: socfpga: Support multiple parents for the pll clocks	Dinh Nguyen	1	-4/+22
2014-02-27	clk: socfpga: Fix integer overflow in clock calculation	Dinh Nguyen	1	-3/+5
2014-02-19	clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"	Dinh Nguyen	1	-0/+68