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path: root/drivers/clk/rockchip
AgeCommit message (Expand)AuthorFilesLines
2021-03-21clk: rockchip: drop MODULE_ALIAS from rk3399 clock controllerHeiko Stuebner1-1/+0
2021-03-21clk: rockchip: drop parenthesis from ARM || COMPILE_TEST dependsHeiko Stuebner1-11/+11
2021-03-21clk: rockchip: add clock controller for rk3568Elaine Zhang4-1/+1762
2021-03-21clk: rockchip: support more core div settingElaine Zhang13-77/+98
2021-02-06clk: rockchip: fix DPHY gate locations on rk3368Heiko Stuebner1-2/+2
2021-02-06clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368Heiko Stuebner1-1/+1
2021-02-06clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368Heiko Stuebner1-2/+2
2021-01-26clk: rockchip: Demote non-conformant kernel-doc header in half-dividerLee Jones1-1/+1
2021-01-26clk: rockchip: Demote kernel-doc abuses to standard comment blocks in pllsLee Jones1-3/+3
2021-01-26clk: rockchip: Remove unused/undocumented struct members from clk-cpuLee Jones1-4/+0
2021-01-26clk: rockchip: Demote non-conformant kernel-doc headers in main clock codeLee Jones1-2/+2
2020-11-29clk: rockchip: fix i2s gate bits on rk3066 and rk3188Johan Jonker1-3/+4
2020-11-29clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocksJohan Jonker1-14/+14
2020-11-29clk: rockchip: Remove redundant null check before clk_prepare_enableXu Wang1-2/+1
2020-10-26clk: rockchip: Add appropriate arch dependenciesRobin Murphy1-1/+11
2020-10-22Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds8-85/+231
2020-10-08clk: rockchip: Initialize hw to error to avoid undefined behaviorStephen Boyd1-1/+1
2020-09-22clk: rockchip: rk3399: Support module buildElaine Zhang2-1/+57
2020-09-22clk: rockchip: fix the clk config to support module buildElaine Zhang2-20/+100
2020-09-22clk: rockchip: Export some clock common APIs for module driversElaine Zhang1-22/+30
2020-09-22clk: rockchip: Export rockchip_register_softrst()Elaine Zhang1-3/+4
2020-09-22clk: rockchip: Export rockchip_clk_register_ddrclk()Elaine Zhang1-0/+1
2020-09-22clk: rockchip: Use clk_hw_register_composite instead of clk_register_composit...Elaine Zhang2-39/+40
2020-09-22clk: rockchip: rk3308: drop unused mux_timer_src_pKrzysztof Kozlowski1-1/+0
2020-08-19clk: rockchip: Fix initialization of mux_pll_src_4plls_pNathan Chancellor1-1/+1
2020-07-22clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocksAlex Bee1-0/+1
2020-07-08clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328"Robin Murphy1-4/+4
2020-07-05clk: rockchip: use separate compatibles for rk3288w-cruHeiko Stuebner1-2/+19
2020-06-17clk: rockchip: Handle clock tree for rk3288w variantMylène Josserand1-2/+18
2020-06-15clk: rockchip: convert rk3036 pll type to use internal lock statusHeiko Stuebner1-3/+23
2020-06-15clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeoutHeiko Stuebner1-15/+6
2020-06-15clk: rockchip: convert rk3399 pll type to use readl_relaxed_poll_timeoutHeiko Stuebner1-11/+12
2020-04-13clk: rockchip: fix incorrect configuration of rk3228 aclk_gpu* clocksJustin Swartz1-13/+4
2020-03-06clk: rockchip: fix mmc get phaseJerome Brunet1-2/+2
2019-12-24clk: let init callback return an error codeJerome Brunet1-11/+17
2019-11-05clk: rockchip: protect the pclk_usb_grf as critical on px30Heiko Stuebner1-1/+2
2019-11-05clk: rockchip: add video-related niu clocks as critical on px30Heiko Stuebner1-5/+10
2019-11-05clk: rockchip: move px30 critical clocks to correct clock controllerHeiko Stuebner1-4/+4
2019-11-05clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandcFinley Xiao1-4/+40
2019-10-31clk: rockchip: make clk_half_divider_ops staticBen Dooks (Codethink)1-2/+1
2019-09-05clk: rockchip: Add clock controller for the rk3308Finley Xiao3-0/+969
2019-07-25clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driverNathan Huckleberry1-1/+0
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds8-46/+27
2019-06-27clk: rockchip: export HDMIPHY clock on rk3228Heiko Stuebner1-1/+1
2019-06-27clk: rockchip: add watchdog pclk on rk3328Heiko Stuebner1-0/+3
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
2019-06-15clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macroHeiko Stuebner4-36/+12
2019-06-14clk: rockchip: add a type from SGRF-controlled gate clocksHeiko Stuebner1-0/+4
2019-06-06clk: rockchip: Remove 48 MHz PLL rate from rk3288Douglas Anderson1-1/+0
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner1-11/+1