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:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
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path:
root
/
drivers
/
clk
/
renesas
Age
Commit message (
Expand
)
Author
Files
Lines
2018-12-15
Merge branch 'clk-of' into clk-next
Stephen Boyd
1
-1
/
+1
2018-12-15
clk: Use of_node_name_eq for node name comparisons
Rob Herring
1
-1
/
+1
2018-12-15
Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '...
Stephen Boyd
9
-34
/
+58
2018-12-11
clk: renesas: Remove usage of CLK_IS_BASIC
Stephen Boyd
5
-8
/
+8
2018-12-07
Merge tag 'clk-renesas-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/...
Stephen Boyd
8
-33
/
+46
2018-12-07
clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
Niklas Söderlund
1
-7
/
+26
2018-12-07
clk: renesas: rcar-gen3: Add documentation for SD clocks
Niklas Söderlund
1
-5
/
+5
2018-12-07
clk: renesas: rcar-gen3: Set state when registering SD clocks
Niklas Söderlund
1
-12
/
+4
2018-12-04
clk: renesas: r8a77995: Simplify PLL3 multiplier/divider
Geert Uytterhoeven
1
-2
/
+2
2018-12-04
clk: renesas: r8a77995: Add missing CPEX clock
Geert Uytterhoeven
1
-1
/
+2
2018-12-04
clk: renesas: r8a77995: Remove non-existent SSP clocks
Geert Uytterhoeven
1
-1
/
+0
2018-12-04
clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks
Geert Uytterhoeven
1
-3
/
+0
2018-12-04
clk: renesas: r8a77995: Correct parent clock of DU
Geert Uytterhoeven
1
-2
/
+2
2018-12-04
clk: renesas: r8a77990: Correct parent clock of DU
Takeshi Kihara
1
-2
/
+2
2018-12-04
clk: renesas: r8a77970: Add CPEX clock
Geert Uytterhoeven
1
-0
/
+1
2018-12-04
clk: renesas: r8a77965: Add CPEX clock
Geert Uytterhoeven
1
-0
/
+1
2018-12-04
clk: renesas: r8a7796: Add CPEX clock
Geert Uytterhoeven
1
-0
/
+1
2018-12-04
clk: renesas: r8a7795: Add CPEX clock
Geert Uytterhoeven
1
-0
/
+1
2018-12-04
clk: renesas: r8a774a1: Add CPEX clock
Geert Uytterhoeven
1
-0
/
+1
2018-11-30
clk: renesas: Mark rza2_cpg_clk_register static
Stephen Boyd
1
-1
/
+1
2018-11-13
clk: renesas: r7s9210: Add USB clocks
Chris Brandt
1
-0
/
+2
2018-11-05
clk: renesas: r8a77970: Add RPC clocks
Sergei Shtylyov
1
-0
/
+4
2018-11-05
clk: renesas: r7s9210: Add SDHI clocks
Chris Brandt
1
-0
/
+5
2018-10-19
Merge branch 'clk-renesas' into clk-next
Stephen Boyd
18
-168
/
+1333
2018-10-19
Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next
Stephen Boyd
10
-28
/
+28
2018-09-29
clk: renesas: Convert to SPDX identifiers
Kuninori Morimoto
21
-89
/
+25
2018-09-28
clk: renesas: r7s9210: Add SPI clocks
Chris Brandt
1
-0
/
+3
2018-09-26
clk: renesas: r7s9210: Move table update to separate function
Chris Brandt
1
-45
/
+50
2018-09-26
clk: renesas: r7s9210: Convert some clocks to early
Chris Brandt
1
-6
/
+26
2018-09-26
clk: renesas: cpg-mssr: Add early clock support
Chris Brandt
2
-21
/
+89
2018-09-25
clk: renesas: r8a77970: Add TPU clock
Sergei Shtylyov
1
-0
/
+1
2018-09-25
clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
Geert Uytterhoeven
1
-2
/
+2
2018-09-19
clk: renesas: cpg-mssr: Add r8a774c0 support
Fabrizio Castro
5
-0
/
+299
2018-09-19
clk: renesas: r8a7743: Add r8a7744 support
Biju Das
3
-2
/
+18
2018-09-11
clk: renesas: cpg-mssr: Add R7S9210 support
Chris Brandt
5
-12
/
+277
2018-09-11
clk: renesas: r8a77970: Add TMU clocks
Sergei Shtylyov
1
-0
/
+5
2018-09-11
clk: renesas: r8a77970: Add CMT clocks
Sergei Shtylyov
1
-0
/
+4
2018-09-11
clk: renesas: r9a06g032: Fix UART34567 clock rate
Phil Edworthy
1
-1
/
+2
2018-09-03
clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI
Sergei Shtylyov
2
-2
/
+67
2018-09-03
clk: renesas: r8a77980: Add CMT clocks
Sergei Shtylyov
1
-0
/
+4
2018-08-31
clk: renesas: r8a77990: Add missing I2C7 clock
Geert Uytterhoeven
1
-0
/
+1
2018-08-31
clk: renesas: use SPDX identifier for Renesas drivers
Wolfram Sang
8
-32
/
+8
2018-08-30
clk: Convert to using %pOFn instead of device_node.name
Rob Herring
10
-28
/
+28
2018-08-28
clk: renesas: r8a77965: Add FDP clock
Hoan Nguyen An
1
-0
/
+1
2018-08-27
clk: renesas: cpg-mssr: Add r8a774a1 support
Biju Das
5
-0
/
+336
2018-08-27
clk: renesas: r8a77965: Add SATA clock
Takeshi Kihara
1
-0
/
+1
2018-08-27
clk: renesas: r8a77980: Add RCLK for watchdog timer
Geert Uytterhoeven
1
-0
/
+4
2018-08-27
clk: renesas: rcar-gen3: Add support for mode pin clock selection
Geert Uytterhoeven
2
-10
/
+13
2018-08-27
clk: renesas: r8a77995: Correct RCLK handling
Geert Uytterhoeven
1
-2
/
+10
2018-08-27
clk: renesas: r8a77990: Correct RCLK handling
Geert Uytterhoeven
1
-2
/
+10
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