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2017-08-24Merge tag 'clk-renesas-for-v4.14-tag1' of ↵Stephen Boyd12-84/+560
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: * Add more module clocks for R-Car V2H and M3-W, * Add support for the R-Car Gen3 USB 2.0 clock selector PHY, * Add support for the new R-Car D3 SoC, * Allow compile-testing of all (sub)drivers now all dummy infrastructure is available, * Small fixes and cleanups. * tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add USB3.0 clock clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY clk: renesas: cpg-mssr: Add R8A77995 support clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3 clk: renesas: Add r8a77995 CPG Core Clock Definitions clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table clk: renesas: rcar-gen3-cpg: Drop superfluous variable clk: renesas: Allow compile-testing of all (sub)drivers clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks clk: renesas: div6: Document fields used for parent selection
2017-08-17clk: renesas: r8a7796: Add USB3.0 clockHiromitsu Yamasaki1-0/+1
This patch adds USB3.0-IF0 clock for R8A7796 SoC. Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-17clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHYYoshihiro Shimoda3-0/+194
R-Car USB 2.0 controller can change the clock source from an oscillator to an external clock via a register. So, this patch adds support the clock source selector as a clock driver. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16clk: renesas: cpg-mssr: Add R8A77995 supportGeert Uytterhoeven5-0/+249
Add R-Car D3 (R8A77995) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 CPG code. Based on the R-Car Series, 3rd Generation Hardware User's Manual, Rev. 0.55, Jun. 30, 2017. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org>
2017-08-16clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocksGeert Uytterhoeven2-1/+26
On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car D3), a peripheral clock divider has been added, to select between clean and spread spectrum parents. Add a new clock type to the R-Car Gen3 driver core to handle this. To avoid increasing the size of struct cpg_core_clk, both parents and dividers are stored in the existing parent resp. div fields. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-16clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3Geert Uytterhoeven4-37/+41
On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider value different from one. Extend struct rcar_gen3_cpg_pll_config to handle this. As all multipliers and dividers are small, table size increase can be kept limited by storing them in u8s instead of unsigned ints, which saves ca. 0.5 KiB for a generic kernel. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-22clk: Convert to using %pOF instead of full_nameRob Herring2-3/+2
Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-omap@vger.kernel.org Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-19clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div tableWolfram Sang1-26/+20
Do the checks for accessing the SD divider table only when the rate gets updated, namely on init and set_rate. In all other cases, reuse the last value. This simplifies code, runtime load, and error reporting. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-19clk: renesas: rcar-gen3-cpg: Drop superfluous variableWolfram Sang1-2/+1
'rate' is not used, so we can use 'parent_rate' directly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17clk: renesas: Allow compile-testing of all (sub)driversGeert Uytterhoeven1-19/+19
Enable compile-testing of the remaining clock drivers and subdrivers, now dummies are available for of_clk_get_from_provider(), of_device_compatible_match(), and rcar_rst_read_mode_pins(), and the CPG/MSSR driver core has been converted from of_match_node() to of_device_get_match_data(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocksGeert Uytterhoeven1-0/+7
Add the module clocks for the Image Renderer Light (SRAM) Extended 3 (IMR-LX3/LSX3) Distortion Correction Engines on R-Car V2H. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17clk: renesas: div6: Document fields used for parent selectionGeert Uytterhoeven1-0/+3
Add the missing documentation for the fields in struct div6_clock related to parent selection for DIV6 clocks with selectable parents, as found in R/SH-Mobile SoCs. Fixes: c6d67fb037f4eaaf ("clk: shmobile: div6: support selectable-input clocks") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-06-20clk: renesas: cpg-mssr: Use of_device_get_match_data() helperGeert Uytterhoeven1-1/+1
If CONFIG_OF=n: drivers/clk/renesas/renesas-cpg-mssr.c: In function ‘cpg_mssr_probe’: drivers/clk/renesas/renesas-cpg-mssr.c:702: warning: dereferencing ‘void *’ pointer drivers/clk/renesas/renesas-cpg-mssr.c:702: error: request for member ‘data’ in something not a structure or union To fix this, use the of_device_get_match_data() helper, for which a dummy version is provided if CONFIG_OF=n. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-05-24clk: renesas: r8a7794: Add new CPG/MSSR driverGeert Uytterhoeven5-2/+266
Add a new R-Car E2 Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-24clk: renesas: r8a7792: Add new CPG/MSSR driverGeert Uytterhoeven5-2/+232
Add a new R-Car V2H Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-24clk: renesas: r8a7791/r8a7793: Add new CPG/MSSR driverGeert Uytterhoeven5-2/+302
Add a new R-Car M2-W/N Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-24clk: renesas: r8a7790: Add new CPG/MSSR driverGeert Uytterhoeven5-1/+298
Add a new R-Car H2 Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-24clk: renesas: Rework Kconfig and Makefile logicGeert Uytterhoeven3-36/+134
The goals are to: - Allow precise control over and automatic selection of which (sub)drivers are used for which SoC (which may change in the future), - Allow adding support for new SoCs easily, - Allow compile-testing of all (sub)drivers, - Keep driver selection logic in the subsystem-specific Kconfig, independent from the architecture-specific Kconfig (i.e. no "select" from arch/arm64/Kconfig.platforms), to avoid dependencies. This is implemented by: - Introducing Kconfig symbols for all drivers and sub-drivers, - Introducing the Kconfig symbol CLK_RENESAS, which is enabled automatically when building for a Renesas ARM platform, and which enables all required drivers without interaction of the user, based on SoC-specific ARCH_* symbols, - Allowing the user to enable any Kconfig symbol manually if COMPILE_TEST is enabled, - Using the new Kconfig symbols instead of the ARCH_* symbols to control compilation in the Makefile, - Always entering drivers/clk/renesas/ during the build. Note that currently not all (sub)drivers are enabled for compile-testing, as they depend on independent fixes in other subsystems. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-05-24clk: renesas: cpg-mssr: Initialize error pointer using ERR_PTR()Geert Uytterhoeven1-1/+1
Coccinelle warns: drivers/clk/renesas/renesas-cpg-mssr.c:323:14-21: ERROR: PTR_ERR applied after initialization to constant on line 260 Initialize clk using ERR_PTR(-ENOTSUPP) instead of NULL to fix this. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7795: Correct pwm, gpio, and i2c parent clocks on ES2.0Geert Uytterhoeven1-13/+26
Cfr. the errata of April 14, 2017, for the R-Car Gen3 Hardware Manual Rev. 0.53E. These have no user-visible effect, as the clock frequencies stay the same. Fixes: 5573d194128b4733 ("clk: renesas: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2017-05-15clk: renesas: Use pm_clk_no_clocks() helper i.s.o. direct accessGeert Uytterhoeven2-2/+2
The pm_subsys_data.clock_list member exists only if CONFIG_PM_CLK=y. Hence direct accesses to this field break compile-testing on platforms where CONFIG_PM_CLK=n. To fix this, use the pm_clk_no_clocks() helper instead, for which a dummy version is provided if CONFIG_PM_CLK=n. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <simon.horman@netronome.com>
2017-05-15clk: renesas: Do not build clk-div6 for R8A7792Geert Uytterhoeven1-1/+1
R-Car V2H does not have "DIV6" programmable clocks, hence there is no need to build clk-div6.o. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2017-05-15clk: renesas: r8a7796: Add INTC-EX clockTakeshi Kihara1-0/+1
Add the "intc-ex" clock to the R8A7796 CPG MSSR driver. According to information from the hardware team the INTC-EX parent clock is CP. The next data sheet version will include this information. [takeshi.kihara.df: Ported from commit f099aa075749 ("clk: shmobile: r8a7795: Add INTC-EX clock") to drivers/clk/renesas/r8a7796-cpg-mssr.c] Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7796: Add PCIe clocksHarunobu Kurokawa1-0/+2
This patch adds PCIEC{0,1} clocks for R8A7796 SoC. Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7796: Add PWM clockRyo Kodama1-0/+1
This patch adds PWM clock for PWM. Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> [geert: Correct parent clock] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7796: Add HS-USB clockKazuya Mizuguchi1-0/+1
This patch adds HS-USB-IF clock for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7796: Add Sound DVC clocksKazuya Mizuguchi1-0/+2
This patch adds adds SCU(DVC{0,1}) clocks for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7796: Add Sound SRC clockKazuya Mizuguchi1-0/+13
This patch adds SCU(all), SCU(SRC{0,1,2,3,4,5,6,7,8,9}), SCU(CTU00, CTU01, CTU02, CTU03, MIX0) and SCU (CTU10, CTU11, CTU12, CTU13, MIX1) clocks for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7796: Add Sound SSI clockKazuya Mizuguchi1-0/+11
This patch adds SSI(all) and SSI{0,1,2,3,4,5,6,7,8,9} clocks for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7796: Add USB-DMAC clocksHiromitsu Yamasaki1-0/+2
This patch adds USB-DMAC{0,1} clocks for R8A7796 SoC. Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7796: Add Audio-DMAC clocksHiromitsu Yamasaki1-0/+2
This patch adds A-DMAC{0,1} clocks for R8A7796 SoC. Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> [geert: Correct parent clocks, preserve sort order] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7796: Add EHCI/OHCI clocksKazuya Mizuguchi1-0/+2
This patch adds EHCI/OHCI{0,1} clocks for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7796: Add HDMI clockKoji Matsuoka1-0/+2
This patch adds HDMI-IF0 clock for R8A7796 SoC. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7795: Add HS-USB ch3 clockTakeshi Kihara1-0/+1
This patch adds valid HS-USB ch3 clock from R8A7795 ES2.0 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7795: Add USB-DMAC ch3 clockTakeshi Kihara1-0/+2
This patch supports the clock of USB-DMAC ch3 module added from R8A7795 ES2.0 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7795: Add EHCI/OHCI ch3 clockTakeshi Kihara1-0/+1
This patch supports the clock of EHCI/OHCI ch3 module added from R8A7795 ES2.0 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7745: Remove PLL configs for MD19=0Geert Uytterhoeven1-11/+2
According to tables 7.5b and 7.6b of the RZ/G Series Hardware User's Manual Rev.1.00, MD19=0 is a prohibited setting. Hence stop looking at MD19, and remove all PLL configurations for MD19=0. Fixes: 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocksGeert Uytterhoeven1-4/+0
RZ/G1E does not have the SCU-SRC[0789] modules and module clocks. Fixes: 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2Geert Uytterhoeven1-4/+19
R-Car V2H and E2 do not have the PLL0CR register, but use a fixed multiplier (depending on mode pins) and divider. This corrects the clock rate of "pll0" (PLL0 VCO after post divider) on R-Car V2H and E2 from 1.5 GHz to 1 GHz. Inspired by Sergei Shtylyov's work for the common R-Car Gen2 and RZ/G Clock Pulse Generator support core. Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree") Fixes: 0dce5454d5c25858 ("ARM: shmobile: Initial r8a7794 SoC device tree") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-30clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0Geert Uytterhoeven1-11/+27
Starting with R-Car H3 ES2.0, the parent of RCLK is selected using MD28. Add support for that, but retain the old behavior for R-Car H3 ES1.x and M3-W ES1.0 using a quirk. Inspired by a patch by Takeshi Kihara in the BSP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
2017-03-30clk: renesas: r8a7795: Add support for R-Car H3 ES2.0Geert Uytterhoeven1-50/+151
The Clock Pulse Generator / Module Standby and Software Reset module in R-Car H3 ES2.0 differs from ES1.x in the following areas: - More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12), - Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR, SYS-DMAC, VIN, VSPB, VSPI, - Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2, USB3-IF1, VSPD3, VSPI2, - Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1. The goal is twofold: 1. Support both the ES1.x and ES2.0 SoC revisions in a single binary for now, 2. Make it clear which code supports ES1.x, so it can easily be identified and removed later, when production SoCs are deemed ubiquitous. This is achieved by: - Updating the clock tables for the latest revision (ES2.0), but not removing clocks that only exist on earlier revisions (ES1.x), - Detecting the SoC revision at runtime using the new soc_device_match() API, and fixing up the clocks tables to match the actual SoC revision, by: - NULLifying core and module clocks of modules that do not exist, - Reparenting module clocks that have a different parent on ES1.x. Based on R-Car Gen3 Hardware User's Manual rev. 0.53E. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-30clk: renesas: cpg-mssr: Add support for fixing up clock tablesGeert Uytterhoeven2-0/+72
The same SoC may have different clocks and/or module clock parents, depending on SoC revision. One option is to use different sets of clock tables for each SoC revision. However, if the differences are small, it is much more space-efficient to have a single set of clock tables, and fix those up at runtime instead. Hence provide three helpers: - Two helpers to NULLify core and module clocks that do not exist on some revisions (NULLified clocks are skipped during the registration phase), - One helper to reparent module clocks that have different clock parents. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0Geert Uytterhoeven1-0/+24
Add a workaround for errata on R-Car H3 ES1.0, where the PLL0, PLL2, and PLL4 clock frequencies are off by a factor of two. Inspired by a patch by Dien Pham in the BSP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Dien Pham <dien.pham.ry@renesas.com>
2017-03-21clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()Geert Uytterhoeven4-4/+6
Pass the mode pin states from the SoC-specific CPG/MSSR driver to the R-Car Gen3 CPG driver core, as their state will be needed to make some core clock configuration decisions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21clk: renesas: r8a7796: Reformat core clock tableGeert Uytterhoeven1-6/+6
For easier comparison with other clock drivers. No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21clk: renesas: r8a7795: Reformat core clock tableGeert Uytterhoeven1-10/+10
For easier comparison with other clock drivers. No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21clk: renesas: r8a7796: Correct name of watchdog clockGeert Uytterhoeven1-1/+1
There's only a single watchdog clock, and it's named "rwdt". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21clk: renesas: r8a7795: Correct name of watchdog clockGeert Uytterhoeven1-1/+1
There's only a single watchdog clock, and it's named "rwdt". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACsGeert Uytterhoeven1-2/+2
The parent clock of the Audio DMACs is the "ZS" AXI bus clock, which maps to S3D1 on R-Car H3 ES1.x. All module clocks must be sorted by clock ID. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
2017-03-06clk: renesas: r8a7796: Add IMR clocksSergei Shtylyov1-0/+2
Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> [geert: Correct parent clocks] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-17 12:33:47 +0300