starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2021-10-15	clk: renesas: r8a779[56]x: Add MLP clocks	Andrey Gusakov	3	-0/+3
2021-10-08	clk: renesas: r9a07g044: Add SDHI clock and reset entries	Biju Das	2	-0/+40
2021-10-08	clk: renesas: rzg2l: Add SDHI clk mux support	Biju Das	2	-0/+130
2021-10-08	clk: renesas: r8a779a0: Add RPC support	Wolfram Sang	1	-0/+32
2021-10-08	clk: renesas: cpg-lib: Move RPC clock registration to the library	Wolfram Sang	3	-87/+92
2021-10-08	clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...	Lad Prabhakar	2	-0/+21
2021-09-28	clk: renesas: r8a779a0: Add Z0 and Z1 clock support	Geert Uytterhoeven	1	-0/+158
2021-09-24	clk: renesas: r9a07g044: Add GbEthernet clock/reset	Biju Das	1	-0/+10
2021-09-24	clk: renesas: rzg2l: Add support to handle coupled clocks	Biju Das	2	-1/+81
2021-09-24	clk: renesas: r9a07g044: Add ethernet clock sources	Biju Das	2	-1/+21
2021-09-24	clk: renesas: rzg2l: Add support to handle MUX clocks	Biju Das	2	-0/+35
2021-09-24	clk: renesas: r8a779a0: Add TPU clock	Wolfram Sang	1	-0/+1
2021-09-24	clk: renesas: rzg2l: Fix clk status function	Biju Das	1	-1/+1
2021-09-24	clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical	Biju Das	1	-0/+2
2021-09-03	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	10	-26/+87
2021-08-29	Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...	Linus Torvalds	1	-1/+1
2021-08-29	clk: renesas: rcar-usb2-clock-sel: Fix kernel NULL pointer dereference	Adam Ford	1	-1/+1
2021-08-13	clk: renesas: Make CLK_R9A06G032 invisible	Geert Uytterhoeven	1	-3/+1
2021-07-26	clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2	Lad Prabhakar	1	-1/+2
2021-07-19	clk: renesas: r9a07g044: Add clock and reset entries for ADC	Lad Prabhakar	1	-0/+6
2021-07-19	clk: renesas: r9a07g044: Add clock and reset entries for CANFD	Lad Prabhakar	1	-0/+4
2021-07-19	clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]	Geert Uytterhoeven	4	-3/+3
2021-07-19	clk: renesas: r9a07g044: Add GPIO clock and reset entries	Lad Prabhakar	1	-0/+5
2021-07-19	clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries	Biju Das	1	-0/+20
2021-07-19	clk: renesas: r9a07g044: Add USB clocks/resets	Biju Das	1	-0/+12
2021-07-19	clk: renesas: r9a07g044: Add DMAC clocks/resets	Biju Das	1	-0/+8
2021-07-19	clk: renesas: r9a07g044: Add I2C clocks/resets	Biju Das	1	-0/+12
2021-07-19	clk: renesas: r8a779a0: Add the DSI clocks	Kieran Bingham	1	-1/+3
2021-07-19	clk: renesas: r8a779a0: Add the DU clock	Kieran Bingham	1	-0/+1
2021-07-19	clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic	Geert Uytterhoeven	4	-4/+4
2021-07-19	clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get()	Lad Prabhakar	1	-1/+1
2021-07-19	clk: renesas: rzg2l: Avoid mixing error pointers and NULL	Dan Carpenter	1	-1/+1
2021-07-19	clk: renesas: rzg2l: Fix a double free on error	Dan Carpenter	1	-7/+1
2021-07-19	clk: renesas: rzg2l: Fix return value and unused assignment	Yang Li	1	-4/+2
2021-07-19	clk: renesas: rzg2l: Remove unneeded semicolon	Yang Li	1	-1/+1
2021-07-12	dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions	Biju Das	3	-64/+93
2021-07-12	clk: renesas: r9a07g044: Add P2 Clock support	Biju Das	2	-0/+5
2021-07-12	clk: renesas: r9a07g044: Fix P1 Clock	Biju Das	1	-3/+3
2021-07-12	clk: renesas: r9a07g044: Rename divider table	Biju Das	1	-3/+4
2021-07-12	clk: renesas: rzg2l: Add multi clock PM support	Biju Das	1	-22/+29
2021-06-10	clk: renesas: Add support for R9A07G044 SoC	Lad Prabhakar	5	-0/+141
2021-06-10	clk: renesas: Add CPG core wrapper for RZ/G2L SoC	Lad Prabhakar	4	-0/+883
2021-05-27	clk: renesas: r8a77995: Add ZA2 clock	Kuninori Morimoto	1	-0/+1
2021-05-27	clk: renesas: cpg-mssr: Make srstclr[] comment block consistent	Geert Uytterhoeven	1	-1/+3
2021-05-27	clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitions	Geert Uytterhoeven	1	-6/+0
2021-05-11	clk: renesas: r9a06g032: Switch to .determine_rate()	Geert Uytterhoeven	1	-12/+13
2021-05-11	clk: renesas: div6: Implement range checking	Geert Uytterhoeven	1	-1/+7
2021-05-11	clk: renesas: div6: Consider all parents for requested rate	Geert Uytterhoeven	1	-3/+32
2021-05-11	clk: renesas: div6: Switch to .determine_rate()	Geert Uytterhoeven	1	-5/+7
2021-05-11	clk: renesas: div6: Simplify src mask handling	Geert Uytterhoeven	1	-20/+11