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path: root/drivers/clk/qcom
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2021-12-21clk: qcom: q6sstop-qcs404: explicitly include clk-provider.hVinod Koul1-0/+1
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211215113803.620032-8-vkoul@kernel.org
2021-12-21clk: qcom: mmcc-apq8084: explicitly include clk-provider.hVinod Koul1-0/+1
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211215113803.620032-7-vkoul@kernel.org
2021-12-21clk: qcom: lpasscc-sdm845: explicitly include clk-provider.hVinod Koul1-0/+1
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211215113803.620032-6-vkoul@kernel.org
2021-12-21clk: qcom: lpasscc-sc7280: explicitly include clk-provider.hVinod Koul1-0/+1
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211215113803.620032-5-vkoul@kernel.org
2021-12-21clk: qcom: gcc-sm6350: explicitly include clk-provider.hVinod Koul1-0/+1
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211215113803.620032-4-vkoul@kernel.org
2021-12-21clk: qcom: gcc-msm8994: explicitly include clk-provider.hVinod Koul1-0/+1
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211215113803.620032-3-vkoul@kernel.org
2021-12-21clk: qcom: gcc-sm8350: explicitly include clk-provider.hVinod Koul1-0/+1
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211215113803.620032-2-vkoul@kernel.org
2021-12-16clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driverAngeloGioacchino Del Regno3-0/+4164
Add support for the global clock controller found on MSM8956 and MSM8976 SoCs. Since the multimedia clocks are actually in the GCC on these SoCs, this will allow drivers to probe and control basically all the required clocks. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211208091036.132334-3-marijn.suijten@somainline.org
2021-12-16clk: qcom: Add clock driver for SM8450Vinod Koul3-0/+3313
This adds Global Clock controller (GCC) driver for SM8450 SoC including the gcc resets and gdsc. This patch is based on initial code downstream by Vivek Aknurwar <viveka@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211207114003.100693-3-vkoul@kernel.org
2021-12-16clk: qcom: Add SDX65 GCC supportVamsi Krishna Lanka3-0/+1620
Add Global Clock Controller (GCC) support for SDX65 SoCs from Qualcomm. Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/b5ea8a00d4e8418b57f4444d0b5243c1acc41808.1638861860.git.quic_vamslank@quicinc.com
2021-12-16clk: qcom: Add LUCID_EVO PLL type for SDX65Vamsi Krishna Lanka2-5/+162
Add a LUCID_EVO PLL type for SDX65 SoC from Qualcomm. Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> [bjorn: Fixed indentation issues reported by checkpatch] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/d582c3e291ae82aa488785eff36157653741f841.1638861860.git.quic_vamslank@quicinc.com
2021-12-07clk: qcom: sm6125-gcc: Swap ops of ice and apps on sdcc1Martin Botka1-2/+2
Without this change eMMC runs at overclocked freq. Swap the ops to not OC the eMMC. Signed-off-by: Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20211130212015.25232-1-martin.botka@somainline.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Fixes: 4b8d6ae57cdf ("clk: qcom: Add SM6125 (TRINKET) GCC driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-12-06clk: qcom: rpmh: add support for SM8450 rpmh clocksVinod Koul1-0/+27
This adds the RPMH clocks present in SM8450 SoC Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201072310.3968679-5-vkoul@kernel.org
2021-12-06clk: qcom: smd-rpm: Drop binary value handling for buffered clockShawn Guo1-8/+0
The buffered clock binary value handling added by commit 36354c32bd76 ("clk: qcom: smd-rpm: Add .recalc_rate hook for clk_smd_rpm_branch_ops") is redundant, because buffered clock is branch type, and the binary value handling for branch clock has been handled by clk_smd_rpm_prepare/unprepare functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211031020715.21636-4-shawn.guo@linaro.org
2021-12-06clk: qcom: smd-rpm: Drop the use of struct rpm_ccShawn Guo1-17/+4
Considering that struct rpm_cc is now identical to rpm_smd_clk_desc, and function qcom_smdrpm_clk_hw_get() uses rpm_cc in a read-only manner, rpm_cc can be dropped by getting the function use rpm_smd_clk_desc directly. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211031020715.21636-3-shawn.guo@linaro.org
2021-12-06clk: qcom: smd-rpm: Drop MFD qcom-rpm referenceShawn Guo1-2/+0
The MFD qcom-rpm interface is not used by this driver. Drop the 'struct qcom_rpm' reference and include of <dt-bindings/mfd/qcom-rpm.h>. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211031020715.21636-2-shawn.guo@linaro.org
2021-12-03clk: qcom: Add support for SDX65 RPMh clocksVamsi krishna Lanka1-0/+25
Add support for clocks maintained by RPMh in SDX65 SoCs. Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/366448562ac52c600c45b5a15129d78b5e8dd5a7.1638402361.git.quic_vamslank@quicinc.com
2021-12-03clk: qcom: clk-alpha-pll: Don't reconfigure running TrionBjorn Andersson1-0/+9
In the event that the bootloader has configured the Trion PLL as source for the display clocks, e.g. for the continuous splashscreen, then there will also be RCGs that are clocked by this instance. Reconfiguring, and in particular disabling the output of, the PLL will cause issues for these downstream RCGs and has been shown to prevent them from being re-parented. Follow downstream and skip configuration if it's determined that the PLL is already running. Fixes: 59128c20a6a9 ("clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20211123162508.153711-1-bjorn.andersson@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-12-03clk: qcom: regmap-mux: fix parent clock lookupDmitry Baryshkov3-1/+15
The function mux_get_parent() uses qcom_find_src_index() to find the parent clock index, which is incorrect: qcom_find_src_index() uses src enum for the lookup, while mux_get_parent() should use cfg field (which corresponds to the register value). Add qcom_find_cfg_index() function doing this kind of lookup and use it for mux parent lookup. Fixes: df964016490b ("clk: qcom: add parent map for regmap mux") Cc: stable@vger.kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20211115233407.1046179-1-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-11-14Merge tag 'clk-for-linus' of ↵Linus Torvalds1-15/+0
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull more clk updates from Stephen Boyd: "This is the second batch of clk driver updates that needed a little more time to soak in linux-next. - Use modern i2c probe in vc5 - Cleanup some includes - Update links to datasheets - Add UniPhier NX1 SoC clk support - Fix DT bindings for SiFive FU740 - Revert the module platform driver support for Rockchip because it wasn't actually tested - Fix the composite clk code again as the previous fix had a one line bug that broke rate changes for clks that want to use the same parent still - Use the right table for a divider in ast2600 driver - Get rid of gcc_aggre1_pnoc_ahb_clk in qcom clk driver again because its critical but unused" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clk clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular composites clk/ast2600: Fix soc revision for AHB clk: composite: Fix 'switching' to same clock clk: rockchip: drop module parts from rk3399 and rk3568 drivers Revert "clk: rockchip: use module_platform_driver_probe" clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.c dt-bindings: clock: fu740-prci: add reset-cells clk: uniphier: Add SoC-glue clock source selector support for Pro4 dt-bindings: clock: uniphier: Add clock binding for SoC-glue clk: uniphier: Add NX1 clock support dt-bindings: clock: uniphier: Add NX1 clock binding clk: uniphier: Add audio system and video input clock control for PXs3 clk: si5351: Update datasheet references clk: vc5: Use i2c .probe_new clk/actions/owl-factor.c: remove superfluous headers clk: ingenic: Fix bugs with divided dividers
2021-11-06clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clkDmitry Baryshkov1-15/+0
The gcc_aggre1_pnoc_ahb_clk is crucial for the proper MSM8996/APQ8096 functioning. If it gets disabled, several subsytems will stop working (including eMMC/SDCC and USB). There are no in-kernel users of this clock, so it is much simpler to remove from the kernel. The clock was first removed in the commit 9e60de1cf270 ("clk: qcom: Remove gcc_aggre1_pnoc_ahb_clk from msm8996") by Stephen Boyd, but got added back in the commit b567752144e3 ("clk: qcom: Add some missing gcc clks for msm8996") by Rajendra Nayak. Let's remove it again in hope that nobody adds it back. Reported-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Fixes: b567752144e3 ("clk: qcom: Add some missing gcc clks for msm8996") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20211104011155.2209654-1-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-11-04Merge tag 'clk-for-linus' of ↵Linus Torvalds22-1299/+7290
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The usual collection of clk driver updates and new driver additions. In terms of lines it's mainly Qualcomm and Mediatek code, supporting various SoCs and their multitude of clk controllers. New Drivers: - GCC and RPMcc support for Qualcomm QCM2290 SoCs - GCC support for Qualcomm MSM8994/MSM8992 SoCs - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs - Support for Mediatek MT8195 SoCs - Initial clock driver for the Exynos850 SoC - Add i.MX8ULP clock driver and related bindings Updates: - Clock power management for new SAMA7G5 SoC - Updates to the master clock driver and sam9x60-pll to be able to use cpufreq-dt driver and avoid overclocking of CPU and MCK0 domains while changing the frequency via DVFS - Use ARRAY_SIZE in qcom clk drivers - Remove some impractical fallback parent names in qcom clk drivers - Make Mediatek clk drivers tristate - Refactoring of the CPU clock code and conversion of Samsung Exynos5433 CPU clock driver to the platform driver - A few conversions to devm_platform_ioremap_resource() - Updates of the Samsung Kconfig help text - Update video path realted clocks for Amlogic meson8 - Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L - Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U - Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N - Remove unused helpers from i.MX specific clock header - Rework all i.MX clk based helpers to use clk_hw based ones - Rework i.MX gate/mux/divider wrappers - Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers - Update i.MX pllv4 and composite clocks to support i.MX8ULP - Disable i.MX7ULP composite clock during initialization - Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite - Disable the i.MX pfd when set pfdv2 clock rate - Add support for i.MX8ULP in pfdv2 - Add the pcc reset controller support on i.MX8ULP - Fix the build break when clk-imx8ulp is built as module - Move csi_sel mux to correct base register in i.MX6UL clock drivr - Fix csi clk gate register in i.MX6UL clock driver - Fix build bug making CLK_IMX8ULP select MXC_CLK - Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U - Add Ethernet clocks on Renesas RZ/G2L - Move Rockchip to use module_platform_probe - Enable usage of Coresight related clocks on Rockchip rk3399" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (170 commits) clk: use clk_core_get_rate_recalc() in clk_rate_get() clk: at91: sama7g5: set low limit for mck0 at 32KHz clk: at91: sama7g5: remove prescaler part of master clock clk: at91: clk-master: add notifier for divider clk: at91: clk-sam9x60-pll: add notifier for div part of PLL clk: at91: clk-master: fix prescaler logic clk: at91: clk-master: mask mckr against layout->mask clk: at91: clk-master: check if div or pres is zero clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL clk: at91: pmc: add sama7g5 to the list of available pmcs clk: at91: clk-master: improve readability by using local variables clk: at91: clk-master: add register definition for sama7g5's master clock clk: at91: sama7g5: add securam's peripheral clock clk: at91: pmc: execute suspend/resume only for backup mode clk: at91: re-factor clocks suspend/resume clk: ux500: Add driver for the reset portions of PRCC dt-bindings: clock: u8500: Rewrite in YAML and extend clk: composite: Use rate_ops.determine_rate when also a mux is available clk: samsung: describe drivers in Kconfig clk: samsung: exynos5433: update apollo and atlas clock probing ...
2021-10-15clk: qcom: gdsc: enable optional power domain supportDmitry Baryshkov2-3/+50
On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Currently we use a regulator to enable this domain on demand, however this has some consequences, as genpd code is not reentrant. Make gdsc code also use pm_runtime calls to ensure that registers are accessible during the gdsc_enable/gdsc_disable operations. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210829154757.784699-6-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-15clk: qcom: videocc-sm8250: use runtime PM for the clock controllerDmitry Baryshkov1-2/+25
On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Use runtime PM calls to make sure that required power domain is powered on while we access clock controller's registers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210829154757.784699-5-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-15clk: qcom: dispcc-sm8250: use runtime PM for the clock controllerDmitry Baryshkov1-2/+25
On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Use runtime PM calls to make sure that required power domain is powered on while we access clock controller's registers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210829154757.784699-4-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: gcc-sc7280: Drop unused arrayStephen Boyd1-6/+0
After commit 3165d1e3c737 ("clk: qcom: gcc: Remove CPUSS clocks control for SC7280") this array is unused. Remove it. Reported-by: kernel test robot <lkp@intel.com> Cc: Taniya Das <tdas@codeaurora.org> Fixes: 3165d1e3c737 ("clk: qcom: gcc: Remove CPUSS clocks control for SC7280") Link: https://lore.kernel.org/r/20211014191259.1689641-1-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: camcc: Add camera clock controller driver for SC7280Taniya Das3-0/+2494
Add support for the camera clock controller found on SC7280 based devices. This would allow camera drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1633567425-11953-2-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Make some VCOs unsigned long] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: Add lpass clock controller driver for SC7280Taniya Das3-0/+225
Add support for the lpass clock controller found on SC7280 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1633484416-27852-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: Kconfig: Sort the symbol for SC_LPASS_CORECC_7180Taniya Das1-9/+9
Fix the order of the Kconfig symbol for SC_LPASS_CORECC_7180. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1633484416-27852-1-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: mmcc-sdm660: Add hw_ctrl flag to venus_core0_gdscAngeloGioacchino Del Regno1-0/+1
As shown downstream[1], this GDSC supports HW trigger mode and we're supposed to enable it in order to ensure correct operation. [1]: https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.6.4.r1/arch/arm/boot/dts/qcom/sdm630.dtsi#L2181 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20211008102041.268253-2-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: mmcc-sdm660: Add necessary CXCs to venus_gdscAngeloGioacchino Del Regno1-0/+2
As also shown on downstream dts[1], for a correct operation of the Venus block, we have to retain MEM/PERIPH when halting the video_core, video_axi and video_subcore0 branches: add these CXCs to the main Venus GDSC. [1]: https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.6.4.r1/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi#L80 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20211008102041.268253-1-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: gcc-msm8994: Use ARRAY_SIZE() for num_parentsKonrad Dybcio1-48/+48
Don't rely on the programmer to enter the name of array elements, since the computer can compute it with much less chance of making a mistake. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-9-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: gcc-msm8994: Add proper msm8992 supportKonrad Dybcio1-1/+70
MSM8992 is a cut-down version of MSM8994, featuring largely the same hardware. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-8-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: gcc-msm8994: Add modem resetKonrad Dybcio1-0/+1
This will be required to support the modem. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-7-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIEKonrad Dybcio1-9/+2
This GDSC is not present on msm8994. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-6-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: gcc-msm8994: Add missing clocksKonrad Dybcio1-0/+134
This should be the last "add missing clocks" commit, as to my knowledge there are no more clocks registered within gcc. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-5-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: gcc-msm8994: Add missing NoC clocksKonrad Dybcio1-12/+89
Add necessary NoC clocks to provide frequency sources for relevant branch clocks. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-4-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: gcc-msm8994: Fix up SPI QUP clocksKonrad Dybcio1-13/+105
Fix up SPI QUP freq tables to account for the fact that not every QUP can run at the same set of frequencies. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-3-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: gcc-msm8994: Modernize the driverKonrad Dybcio1-555/+305
Switch to the newer-style parent_data and remove the hardcoded xo clock. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-2-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: smd-rpm: Add QCM2290 RPM clock supportShawn Guo1-0/+59
Add support for RPM-managed clocks on the QCM2290 platform. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210917030434.19859-4-shawn.guo@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: smd-rpm: Add .recalc_rate hook for clk_smd_rpm_branch_opsShawn Guo1-33/+43
As there is a `rate` field in clk_smd_rpm, clk_smd_rpm_recalc_rate() can be used by branch clocks to report rate as well, rather than assuming the rate is always same as parent clock. This assumption doesn't hold on platforms like QCM2290, where xo_board is 38.4MHz while bi_tcxo is 19.2MHz. To get this work, XO buffered clocks need the following updates. - Assign a correct rate rather than the fake one which is being used to generate binary value for clk_smd_rpm_req interface. - Explicitly handle the clk_smd_rpm_req interface value for XO buffered clocks (.rpm_res_type being QCOM_SMD_RPM_CLK_BUF_A). Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210917030434.19859-2-shawn.guo@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> [sboyd@kernel.org: Do cpu_to_le32() again to keep sparse happy] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: Add Global Clock Controller driver for QCM2290Shawn Guo3-0/+3053
Add Global Clock Controller (GCC) driver for QCM2290. This is a porting of gcc-scuba driver from CAF msm-4.19, with GDSC support added on top. Because the alpha_pll on the platform has a different register layout (offsets), its own clk_alpha_pll_regs_offset[] is used in the driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210919023308.24498-3-shawn.guo@linaro.org Acked-by: Rob Herring <robh@kernel.org> [sboyd@kernel.org: Drop duplicate includes, clk.h include, module alias] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: add select QCOM_GDSC for SM6350Luca Weiss1-0/+1
QCOM_GDSC is needed for the gcc driver to probe. Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver") Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20211007212444.328034-2-luca@z3ntu.xyz Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: gcc-sm6115: Fix offset for hlos1_vote_turing_mmu_tbu0_gdscShawn Guo1-1/+1
It looks that the offset 0x7d060 is a copy & paste from above hlos1_vote_turing_mmu_tbu1_gdsc. Correct it to 0x7d07c as per downstream kernel. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210919022308.24046-1-shawn.guo@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-08clk: qcom: gcc: Remove CPUSS clocks control for SC7280Taniya Das1-79/+0
The CPUSS clocks are kept always ON and at a fixed frequency of 100MHZ from the bootloader and no longer required to be controlled from HLOS. Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1633579571-25475-1-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-08clk: qcom: Remove redundant .ownerKai Song1-1/+0
Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: Kai Song <songkai01@inspur.com> Link: https://lore.kernel.org/r/20211006043627.5125-1-songkai01@inspur.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-15clk: qcom: mmcc-msm8998: Remove unnecessary fallbacks to global clocksMarijn Suijten1-57/+48
A previous patch removes the "xo" clock from the global namespace making it impossible to acquire by that ".name". The device-tree for msm8998 currently does not include an mmcc node but the dt-bindings for this compatible already require all these clocks, and the patch introducing this node [1] also includes them. [1]: https://patchwork.kernel.org/project/linux-arm-msm/patch/20210901183123.1087392-1-angelogioacchino.delregno@somainline.org/ Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210911121340.261920-9-marijn.suijten@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-15clk: qcom: gpucc-msm8998: Remove unnecessary fallbacks to global clocksMarijn Suijten1-3/+2
A previous patch removes the "xo" clock from the global namespace making it impossible to acquire by that ".name". The device-tree for msm8998 already provides the "xo" and "gpll0" clock since the addition of the gpucc node making it unnecessary to have this fallback at all. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210911121340.261920-8-marijn.suijten@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-15clk: qcom: mmcc-msm8998: Use ARRAY_SIZE for num_parentsMarijn Suijten1-39/+39
Where possible, use ARRAY_SIZE to determine the number of parents in clk_parent_data, instead of hardcoding it. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210911121340.261920-6-marijn.suijten@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-15clk: qcom: gpucc-msm8998: Use ARRAY_SIZE for num_parentsMarijn Suijten1-4/+4
Where possible, use ARRAY_SIZE to determine the number of parents in clk_parent_data, instead of hardcoding it. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210911121340.261920-5-marijn.suijten@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 22:10:01 +0300