starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2015-08-26	clk: pistachio: correct critical clock list	Damien.Horsley	1	-5/+14
2015-08-26	clk: pistachio: Fix PLL rate calculation in integer mode	Zdenko Pulitika	1	-2/+46
2015-08-26	clk: pistachio: Fix override of clk-pll settings from boot loader	Zdenko Pulitika	1	-3/+2
2015-08-26	clk: pistachio: Fix 32bit integer overflows	Zdenko Pulitika	2	-21/+19
2015-08-25	clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)	Stephen Boyd	1	-2/+2
2015-07-20	clk: pistachio: Include clk.h	Stephen Boyd	1	-0/+1
2015-06-04	clk: pistachio: Add sanity checks on PLL configuration	Kevin Cernekee	1	-4/+79
2015-06-04	clk: pistachio: Lock the PLL when enabled upon rate change	Ezequiel Garcia	1	-18/+10
2015-06-04	clk: pistachio: Add a pll_lock() helper for clarity	Ezequiel Garcia	1	-4/+8
2015-03-31	CLK: Pistachio: Register external clock gates	Andrew Bresticker	1	-0/+21
2015-03-31	CLK: Pistachio: Register system interface gate clocks	Andrew Bresticker	1	-0/+42
2015-03-31	CLK: Pistachio: Register peripheral clocks	Andrew Bresticker	1	-0/+67
2015-03-31	CLK: Pistachio: Register core clocks	Andrew Bresticker	2	-0/+200
2015-03-31	CLK: Pistachio: Add PLL driver	Andrew Bresticker	3	-0/+452
2015-03-31	CLK: Add basic infrastructure for Pistachio clocks	Andrew Bresticker	3	-0/+265