starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2018-05-21	clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL	Martin Blumenstingl	1	-0/+7
2018-05-18	clk: meson: use SPDX license identifiers consistently	Jerome Brunet	1	-15/+1
2018-05-15	clk: meson: meson8b: add support for the NAND clocks	Martin Blumenstingl	1	-0/+54
2018-04-25	clk: meson: meson8b: fix meson8b_cpu_clk parent clock name	Martin Blumenstingl	1	-1/+2
2018-04-25	clk: meson: meson8b: fix meson8b_fclk_div3_div clock name	Martin Blumenstingl	1	-1/+1
2018-03-15	clk: meson: Drop unused local variable and add static	Stephen Boyd	1	-7/+6
2018-03-13	clk: meson: clean-up clk81 clocks	Jerome Brunet	1	-4/+2
2018-03-13	clk: meson: add fdiv clock gates	Jerome Brunet	1	-10/+85
2018-03-13	clk: meson: add mpll pre-divider	Jerome Brunet	1	-3/+19
2018-03-13	clk: meson: add fractional part of meson8b fixed_pll	Jerome Brunet	1	-0/+5
2018-03-13	clk: meson: rework meson8b cpu clock	Jerome Brunet	1	-60/+113
2018-03-13	clk: meson: split divider and gate part of mpll	Jerome Brunet	1	-21/+54
2018-03-13	clk: meson: migrate plls clocks to clk_regmap	Jerome Brunet	1	-62/+87
2018-03-13	clk: meson: migrate mplls clocks to clk_regmap	Jerome Brunet	1	-78/+77
2018-03-13	clk: meson: migrate muxes to clk_regmap	Jerome Brunet	1	-18/+9
2018-03-13	clk: meson: migrate dividers to clk_regmap	Jerome Brunet	1	-15/+8
2018-03-13	clk: meson: migrate gates to clk_regmap	Jerome Brunet	1	-19/+20
2018-03-13	clk: meson: add regmap to the clock controllers	Jerome Brunet	1	-1/+13
2018-03-13	clk: meson: remove obsolete comments	Jerome Brunet	1	-1/+0
2018-03-13	clk: meson: only one loop index is necessary in probe	Jerome Brunet	1	-4/+4
2018-03-13	clk: meson: use devm_of_clk_add_hw_provider	Jerome Brunet	1	-2/+2
2017-12-14	clk: meson: make the spinlock naming more specific	Yixun Lan	1	-12/+12
2017-08-24	Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into cl...	Stephen Boyd	1	-12/+148
2017-08-04	clk: meson: meson8b: register the built-in reset controller	Martin Blumenstingl	1	-12/+147
2017-08-04	clk: meson: meson8b: fix protection against undefined clks	Jerome Brunet	1	-0/+1
2017-08-01	clk: meson: mpll: fix mpll0 fractional part ignored	Jerome Brunet	1	-0/+5
2017-06-12	clk: meson: meson8b: add compatibles for Meson8 and Meson8m2	Martin Blumenstingl	1	-1/+4
2017-05-29	clk: meson: meson8b: mark clk81 as critical	Martin Blumenstingl	1	-1/+1
2017-03-27	clk: meson8b: add the mplls clocks 0, 1 and 2	Jerome Brunet	1	-0/+103
2017-03-27	clk: meson8b: put dividers and muxes in tables	Jerome Brunet	1	-4/+18
2017-03-27	clk: meson: add missing const qualifiers on gate arrays	Jerome Brunet	1	-1/+1
2017-01-27	clk: meson8b: fix clk81 register address	Jerome Brunet	1	-1/+0
2016-09-14	clk: meson: fix CLKID_GCLK_VENCI_INT typo	Arnd Bergmann	1	-1/+1
2016-09-14	meson: clk: Use builtin_platform_driver to simplify the code	Wei Yongjun	1	-5/+1
2016-09-02	meson: clk: Add support for clock gates	Alexander Müller	1	-0/+249
2016-09-02	clk: meson: Copy meson8b CLKID defines to private header file	Alexander Müller	1	-1/+0
2016-09-02	meson: clk: Rename register names according to Amlogic datasheet	Alexander Müller	1	-13/+13
2016-09-02	meson: clk: Move register definitions to meson8b.h	Alexander Müller	1	-16/+1
2016-09-02	clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention	Alexander Müller	1	-0/+447