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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
meson
/
clk-pll.c
Age
Commit message (
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Author
Files
Lines
2019-05-07
Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be'...
Stephen Boyd
1
-0
/
+26
2019-04-01
clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
Neil Armstrong
1
-0
/
+26
2019-03-25
clk: meson: pll: fix rounding and setting a rate that matches precisely
Martin Blumenstingl
1
-1
/
+1
2019-02-04
clk: meson: pll: update driver for the g12a
Jerome Brunet
1
-57
/
+146
2019-02-02
clk: meson: rework and clean drivers dependencies
Jerome Brunet
1
-4
/
+9
2018-11-23
clk: meson: clk-pll: check if the clock is already enabled
Martin Blumenstingl
1
-0
/
+19
2018-09-26
clk: meson: clk-pll: drop hard-coded rates from pll tables
Jerome Brunet
1
-23
/
+46
2018-09-26
clk: meson: clk-pll: remove od parameters
Jerome Brunet
1
-27
/
+13
2018-09-26
clk: meson: clk-pll: add enable bit
Jerome Brunet
1
-5
/
+42
2018-05-18
clk: meson: use SPDX license identifiers consistently
Jerome Brunet
1
-12
/
+1
2018-03-13
clk: meson: add ROUND_CLOSEST to the pll driver
Jerome Brunet
1
-4
/
+13
2018-03-13
clk: meson: improve pll driver results with frac
Jerome Brunet
1
-47
/
+90
2018-03-13
clk: meson: remove special gp0 lock loop
Jerome Brunet
1
-11
/
+1
2018-03-13
clk: meson: migrate plls clocks to clk_regmap
Jerome Brunet
1
-150
/
+93
2018-02-12
clk: meson: fix rate calculation of plls with a fractional part
Jerome Brunet
1
-1
/
+0
2018-02-12
clk: meson: add od3 to the pll driver
Jerome Brunet
1
-3
/
+16
2018-02-12
clk: meson: use the frac parameter width instead of a constant
Jerome Brunet
1
-1
/
+1
2018-02-12
clk: meson: remove unnecessary rounding in the pll clock
Jerome Brunet
1
-8
/
+9
2018-02-12
clk: meson: check pll rate param table before using it
Jerome Brunet
1
-0
/
+10
2017-04-04
clk: meson: Add support for parameters for specific PLLs
Neil Armstrong
1
-2
/
+51
2016-06-23
clk: meson: fractional pll support
Michael Turquette
1
-2
/
+30
2016-06-23
clk: meson8b: clean up pll clocks
Michael Turquette
1
-61
/
+11
2015-06-06
clk: meson: Add support for Meson clock controller
Carlo Caione
1
-0
/
+227