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2022-12-31clk: mediatek: fix dependency of MT7986 ADC clocksDaniel Golle1-1/+1
[ Upstream commit a46315295489933209e902638cd287aeb5f982ab ] It seems like CLK_INFRA_ADC_FRC_CK always need to be enabled for CLK_INFRA_ADC_26M_CK to work. Instead of adding this dependency to the mtk-thermal and mt6577_auxadc drivers, add dependency to the clock driver clk-mt7986-infracfg.c. Fixes: ec97d23c8e22 ("clk: mediatek: add mt7986 clock support") Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/5e55012567da74870e1fb2edc2dc513b5821e523.1666801017.git.daniel@makrotopia.org Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-10-18clk: mediatek: clk-mt8195-topckgen: Fix error return code in ↵Yang Yingliang1-1/+3
clk_mt8195_topck_probe() If devm_clk_hw_register_mux() fails in clk_mt8195_topck_probe(), it should return error code. Fixes: deeb2af77cf6 ("clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20221009025056.35311-1-yangyingliang@huawei.com Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-10-14Merge branch 'clk-rate-range' into clk-nextStephen Boyd1-0/+10
- Various clk rate range fixes - Drop clk rate range constraints on clk_put() (redux) * clk-rate-range: (28 commits) clk: mediatek: clk-mux: Add .determine_rate() callback clk: tests: Add tests for notifiers clk: Update req_rate on __clk_recalc_rates() clk: tests: Add missing test case for ranges clk: qcom: clk-rcg2: Take clock boundaries into consideration for gfx3d clk: Introduce the clk_hw_get_rate_range function clk: Zero the clk_rate_request structure clk: Stop forwarding clk_rate_requests to the parent clk: Constify clk_has_parent() clk: Introduce clk_core_has_parent() clk: Switch from __clk_determine_rate to clk_core_round_rate_nolock clk: Add our request boundaries in clk_core_init_rate_req clk: Introduce clk_hw_init_rate_request() clk: Move clk_core_init_rate_req() from clk_core_round_rate_nolock() to its caller clk: Change clk_core_init_rate_req prototype clk: Set req_rate on reparenting clk: Take into account uncached clocks in clk_set_rate_range() clk: tests: Add some tests for orphan with multiple parents clk: tests: Add tests for mux with multiple parents clk: tests: Add tests for single parent mux ...
2022-10-14clk: mediatek: clk-mux: Add .determine_rate() callbackAngeloGioacchino Del Regno1-0/+10
Since commit 262ca38f4b6e ("clk: Stop forwarding clk_rate_requests to the parent"), the clk_rate_request is .. as the title says, not forwarded anymore to the parent: this produces an issue with the MediaTek clock MUX driver during GPU DVFS on MT8195, but not on MT8192 or others. This is because, differently from others, like MT8192 where all of the clocks in the MFG parents tree are of mtk_mux type, but in the parent tree of MT8195's MFG clock, we have one mtk_mux clock and one (clk framework generic) mux clock, like so: names: mfg_bg3d -> mfg_ck_fast_ref -> top_mfg_core_tmp (or) mfgpll types: mtk_gate -> mux -> mtk_mux (or) mtk_pll To solve this issue and also keep the GPU DVFS clocks code working as expected, wire up a .determine_rate() callback for the mtk_mux ops; for that, the standard clk_mux_determine_rate_flags() was used as it was possible to. This commit was successfully tested on MT6795 Xperia M5, MT8173 Elm, MT8192 Spherion and MT8195 Tomato; no regressions were seen. For the sake of some more documentation about this issue here's the trace of it: [ 12.211587] ------------[ cut here ]------------ [ 12.211589] WARNING: CPU: 6 PID: 78 at drivers/clk/clk.c:1462 clk_core_init_rate_req+0x84/0x90 [ 12.211593] Modules linked in: stp crct10dif_ce mtk_adsp_common llc rfkill snd_sof_xtensa_dsp panfrost(+) sbs_battery cros_ec_lid_angle cros_ec_sensors snd_sof_of cros_ec_sensors_core hid_multitouch cros_usbpd_logger snd_sof gpu_sched snd_sof_utils fuse ipv6 [ 12.211614] CPU: 6 PID: 78 Comm: kworker/u16:2 Tainted: G W 6.0.0-next-20221011+ #58 [ 12.211616] Hardware name: Acer Tomato (rev2) board (DT) [ 12.211617] Workqueue: devfreq_wq devfreq_monitor [ 12.211620] pstate: 40400009 (nZcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 12.211622] pc : clk_core_init_rate_req+0x84/0x90 [ 12.211625] lr : clk_core_forward_rate_req+0xa4/0xe4 [ 12.211627] sp : ffff80000893b8e0 [ 12.211628] x29: ffff80000893b8e0 x28: ffffdddf92f9b000 x27: ffff46a2c0e8bc05 [ 12.211632] x26: ffff46a2c1041200 x25: 0000000000000000 x24: 00000000173eed80 [ 12.211636] x23: ffff80000893b9c0 x22: ffff80000893b940 x21: 0000000000000000 [ 12.211641] x20: ffff46a2c1039f00 x19: ffff46a2c1039f00 x18: 0000000000000000 [ 12.211645] x17: 0000000000000038 x16: 000000000000d904 x15: 0000000000000003 [ 12.211649] x14: ffffdddf9357ce48 x13: ffffdddf935e71c8 x12: 000000000004803c [ 12.211653] x11: 00000000a867d7ad x10: 00000000a867d7ad x9 : ffffdddf90c28df4 [ 12.211657] x8 : ffffdddf9357a980 x7 : 0000000000000000 x6 : 0000000000000004 [ 12.211661] x5 : ffffffffffffffc8 x4 : 00000000173eed80 x3 : ffff80000893b940 [ 12.211665] x2 : 00000000173eed80 x1 : ffff80000893b940 x0 : 0000000000000000 [ 12.211669] Call trace: [ 12.211670] clk_core_init_rate_req+0x84/0x90 [ 12.211673] clk_core_round_rate_nolock+0xe8/0x10c [ 12.211675] clk_mux_determine_rate_flags+0x174/0x1f0 [ 12.211677] clk_mux_determine_rate+0x1c/0x30 [ 12.211680] clk_core_determine_round_nolock+0x74/0x130 [ 12.211682] clk_core_round_rate_nolock+0x58/0x10c [ 12.211684] clk_core_round_rate_nolock+0xf4/0x10c [ 12.211686] clk_core_set_rate_nolock+0x194/0x2ac [ 12.211688] clk_set_rate+0x40/0x94 [ 12.211691] _opp_config_clk_single+0x38/0xa0 [ 12.211693] _set_opp+0x1b0/0x500 [ 12.211695] dev_pm_opp_set_rate+0x120/0x290 [ 12.211697] panfrost_devfreq_target+0x3c/0x50 [panfrost] [ 12.211705] devfreq_set_target+0x8c/0x2d0 [ 12.211707] devfreq_update_target+0xcc/0xf4 [ 12.211708] devfreq_monitor+0x40/0x1d0 [ 12.211710] process_one_work+0x294/0x664 [ 12.211712] worker_thread+0x7c/0x45c [ 12.211713] kthread+0x104/0x110 [ 12.211716] ret_from_fork+0x10/0x20 [ 12.211718] irq event stamp: 7102 [ 12.211719] hardirqs last enabled at (7101): [<ffffdddf904ea5a0>] finish_task_switch.isra.0+0xec/0x2f0 [ 12.211723] hardirqs last disabled at (7102): [<ffffdddf91794b74>] el1_dbg+0x24/0x90 [ 12.211726] softirqs last enabled at (6716): [<ffffdddf90410be4>] __do_softirq+0x414/0x588 [ 12.211728] softirqs last disabled at (6507): [<ffffdddf904171d8>] ____do_softirq+0x18/0x24 [ 12.211730] ---[ end trace 0000000000000000 ]--- Fixes: 262ca38f4b6e ("clk: Stop forwarding clk_rate_requests to the parent") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221011135548.318323-1-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-10-01clk: mediatek: add driver for MT8365 SoCFabien Parent9-0/+1614
Add clock drivers for MT8365 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220822152652.3499972-5-msp@baylibre.com Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-10-01clk: mediatek: Export required common code symbolsMarkus Schneider-Pargmann1-0/+2
To make clk-mt8365 compilable as a module there are a few function symbols missing. This patch adds the required EXPORT_SYMBOL_GPL to the functions. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220822152652.3499972-4-msp@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-10-01clk: mediatek: Provide mtk_devm_alloc_clk_dataMarkus Schneider-Pargmann2-5/+30
Provide a helper that replaces the kzalloc with devm_kzalloc so error handling gets easier. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220822152652.3499972-3-msp@baylibre.com Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-29clk: mediatek: mt8192: deduplicate parent clock listsChen-Yu Tsai1-181/+25
Some groups of clocks of the same type share the same list of parents. These lists were declared separately for each clock in older drivers, bloating the code. Merge some obvious duplicate parent clock lists in the MT8192 clock driver together to reduce the code size. These include: - apll_i2s*_m_parents into one as apll_i2s_m_parents - img1_parents & img2_parents into one as img_parents - msdc30_*_parents into one as msdc30_parents - camtg*_parents into cam_tg_parents - seninf*_parents into seninf_parents Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220926102523.2367530-6-wenst@chromium.org Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-29clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*()Chen-Yu Tsai1-5/+5
During the previous |struct clk| to |struct clk_hw| clk provider API migration in commit 6f691a586296 ("clk: mediatek: Switch to clk_hw provider APIs"), a few clk_unregister_*() calls were missed. Migrate the remaining ones to the |struct clk_hw| provider API, i.e. change clk_unregister_*() to clk_hw_unregister_*(). Fixes: 6f691a586296 ("clk: mediatek: Switch to clk_hw provider APIs") Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220926102523.2367530-3-wenst@chromium.org Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-29clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanupChen-Yu Tsai1-1/+1
When the cleanup paths for the various clk register APIs in the MediaTek clk library were added, the one in the dividers type used the wrong type of unregister function. This would result in incorrect dereferencing of the clk pointer and freeing of invalid pointers. Fix this by switching to the correct type of clk unregistration call. Fixes: 3c3ba2ab0226 ("clk: mediatek: mtk: Implement error handling in register APIs") Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220926102523.2367530-2-wenst@chromium.org Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-29clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_selAngeloGioacchino Del Regno1-0/+28
Following the changes that were done for mt8183, add a clock notifier for the GPU PLL selector mux: this allows safe clock rate changes by temporarily reparenting the GPU to a safe clock (clk26m) while the MFGPLL is reprogrammed and stabilizes. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220927101128.44758-11-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-29clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parentAngeloGioacchino Del Regno1-2/+4
Following what was done on MT8183 and MT8195, also propagate the rate changes to MFG_BG3D's parent on MT8192 to allow for proper GPU DVFS. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220927101128.44758-10-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-29clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parentsAngeloGioacchino Del Regno1-3/+6
These PLLs are conflicting with GPU rates that can be generated by the GPU-dedicated MFGPLL and would require a special clock handler to be used, for very little and ignorable power consumption benefits. Also, we're in any case unable to set the rate of these PLLs to something else that is sensible for this task, so simply drop them: this will make the GPU to be clocked exclusively from MFGPLL for "fast" rates, while still achieving the right "safe" rate during PLL frequency locking. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220927101128.44758-9-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-29clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifierAngeloGioacchino Del Regno1-0/+20
Following the changes done to MT8183, register a similar notifier for MT8195 as well, allowing safe clockrate updates for the MFGPLL. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220927101128.44758-8-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-29clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic muxAngeloGioacchino Del Regno1-12/+7
This clock was being registered as clk-composite through the helpers for the same in the MediaTek clock APIs but, in reality, this isn't a composite clock. Appropriately register this clock with devm_clk_hw_register_mux(). No functional changes. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220927101128.44758-7-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-29clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changesAngeloGioacchino Del Regno1-2/+4
The MFG_BG3D is a gate to enable/disable clock output to the GPU, but the actual output is decided by multiple muxes; in particular: mfg_ck_fast_ref muxes between "slow" (top_mfg_core_tmp) and "fast" (MFGPLL) clock, while top_mfg_core_tmp muxes between the 26MHz clock and various system PLLs. The clock gate comes after all the muxes, so its parent is mfg_ck_fast_reg, not top_mfg_core_tmp. Reparent MFG_BG3D to the latter to match the hardware and add the CLK_SET_RATE_PARENT flag to it: this way we ensure propagating rate changes that are requested on MFG_BG3D along its entire clock tree. Fixes: 35016f10c0e5 ("clk: mediatek: Add MT8195 mfgcfg clock support") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220927101128.44758-6-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-29clk: mediatek: mt8183: Add clk mux notifier for MFG muxChen-Yu Tsai1-0/+28
When the MFG PLL clock, which is upstream of the MFG clock, is changed, the downstream clock and consumers need to be switched away from the PLL over to a stable clock to avoid glitches. This is done through the use of the newly added clk mux notifier. The notifier is set on the mux itself instead of the upstream PLL, but in practice this works, as the rate change notifitcations are propogated throughout the sub-tree hanging off the PLL. Just before rate changes, the MFG mux is temporarily and transparently switched to the 26 MHz main crystal. After the rate change, the mux is switched back. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> [Angelo: Rebased to assign clk_ops in mtk_mux_nb] Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220927101128.44758-5-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-29clk: mediatek: mux: add clk notifier functionsChen-Yu Tsai2-0/+53
With device frequency scaling, the mux clock that (indirectly) feeds the device selects between a dedicated PLL, and some other stable clocks. When a clk rate change is requested, the (normally) upstream PLL is reconfigured. It's possible for the clock output of the PLL to become unstable during this process. To avoid causing the device to glitch, the mux should temporarily be switched over to another "stable" clock during the PLL rate change. This is done with clk notifiers. This patch adds common functions for notifiers to temporarily and transparently reparent mux clocks. This was loosely based on commit 8adfb08605a9 ("clk: sunxi-ng: mux: Add clk notifier functions"). Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> [Angelo: Changed mtk_mux_nb to hold a pointer to clk_ops instead of mtk_mux] Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220927101128.44758-4-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-29clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parentChen-Yu Tsai1-3/+3
The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its rate change requests to its parent, so that DVFS for the GPU can work properly. Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220927101128.44758-3-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probeYassine Oudjana1-1/+2
Register gates with dev in mtk_clk_simple_probe. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220813083319.45455-1-y.oudjana@protonmail.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: gate: Export mtk_clk_register_gates_with_devYassine Oudjana1-0/+1
This allows it to be used in drivers built as modules. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220813083249.45427-1-y.oudjana@protonmail.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: add VDOSYS1 clockPablo Sun1-0/+11
Add the clock gate definition for the DPI1 hardware in VDOSYS1. The parent clock "hdmi_txpll" is already defined in `mt8195.dtsi`. Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220919-v1-2-4844816c9808@baylibre.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: mt8192: add mtk_clk_simple_removeMiles Chen10-0/+10
mt8192 is already using mtk_clk_simple_probe, but not mtk_clk_simple_remove. Let's add mtk_clk_simple_remove for mt8192. Signed-off-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220922091841.4099-8-miles.chen@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: mt8183: use mtk_clk_simple_probe to simplify driverMiles Chen9-137/+108
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220922091841.4099-7-miles.chen@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: mt6797: use mtk_clk_simple_probe to simplify driverMiles Chen3-69/+39
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220922091841.4099-6-miles.chen@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: mt6779: use mtk_clk_simple_probe to simplify driverMiles Chen7-111/+90
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220922091841.4099-5-miles.chen@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: mt6765: use mtk_clk_simple_probe to simplify driverMiles Chen6-129/+72
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220922091841.4099-4-miles.chen@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: mt2712: use mtk_clk_simple_probe to simplify driverMiles Chen6-132/+72
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220922091841.4099-3-miles.chen@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: mt2701: use mtk_clk_simple_probe to simplify driverMiles Chen3-69/+39
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220922091841.4099-2-miles.chen@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: Add MediaTek Helio X10 MT6795 clock driversAngeloGioacchino Del Regno10-0/+1408
Add the clock drivers for the entire clock tree of MediaTek Helio X10 MT6795, including system clocks (apmixedsys, infracfg, pericfg, topckgen) and multimedia clocks (mmsys, mfg, vdecsys, vencsys). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220921091455.41327-9-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: clk-apmixed: Add helper function to unregister ref2usb_txAngeloGioacchino Del Regno2-0/+10
The ref2usb_tx clock was introduced a long time ago and, at that time, the MediaTek clock drivers were using CLK_OF_DECLARE, so they would never unregister. Nowadays, unregistering clock drivers is a thing, as we're registering them as platform_driver and allowing them to be kernel modules: add a helper function to cleanup the ref2usb_tx clock during error handling and upon module removal. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220921091455.41327-8-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: Export required symbols to compile clk drivers as moduleAngeloGioacchino Del Regno4-0/+6
In order to compile the clock drivers for various MediaTek SoCs as modules, it is necessary to export a few functions from the MediaTek specific clocks (and reset) libraries. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220921091455.41327-7-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-26clk: mediatek: clk-apmixed: Remove unneeded __init annotationAngeloGioacchino Del Regno1-1/+1
Remove an unneeded __init annotation from the declaration of function mtk_clk_register_ref2usb_tx(): this avoids section mismatch warnings during modpost phase when called from functions that have no such annotation (useful when clocks are platform drivers). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220921091455.41327-6-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
2022-09-01clk: mediatek: mt8195: Add reset idx for USB/PCIe T-PHYAngeloGioacchino Del Regno1-0/+1
Add the reset idx for the t-phy port 1, used as either USB or PCI-Express (secondary controller) PHY, depending on board-specific configuration/layout. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220720102817.237483-3-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-01clk: mediatek: mt8195-infra_ao: Set pwrmcu clocks as criticalAngeloGioacchino Del Regno1-3/+10
The pwrmcu is responsible for power management and idle states in SSPM: on older SoCs this was managed in Linux drivers like sspm/mcupm/eemgpu but, at least on MT8195, this functionality was transferred to the ATF firmware. For this reason, turning off the pwrmcu related clocks from the kernel will lead to unability to resume the platform after suspend and other currently unknown PM related side-effects. Set the PWRMCU and PWRMCU_BUS_H clocks as critical to prevent the kernel from turning them off, fixing the aforementioned issue. Fixes: e2edf59dec0b ("clk: mediatek: Add MT8195 infrastructure clock support") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220719093316.37253-1-angelogioacchino.delregno@collabora.com Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-01clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1AngeloGioacchino Del Regno1-0/+2
Add the reset idx for PCIe P0, P1, located in infra_ao RST2 registers. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220629105205.173471-3-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-08-31clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parentAngeloGioacchino Del Regno1-1/+5
Like it was done for the vdo0_dp_intf0_dp_intf clock (used for eDP), add the CLK_SET_RATE_PARENT flag to CLK_VDO1_DPINTF (used for DP) and also fix its parent clock name as it has to be "top_dp" for two reasons: - This is its real parent! - Likewise to eDP/VDO0 counterpart, we need clock source selection on CLK_TOP_DP. Fixes: 269987505ba9 ("clk: mediatek: Add MT8195 vdosys1 clock support") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220816193257.658487-3-nfraprado@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-08-31clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parentAngeloGioacchino Del Regno1-1/+6
Add the CLK_SET_RATE_PARENT flag to the CLK_VDO0_DP_INTF0_DP_INTF clock: this is required to trigger clock source selection on CLK_TOP_EDP, while avoiding to manage the enablement of the former separately from the latter in the displayport driver. Fixes: 70282c90d4a2 ("clk: mediatek: Add MT8195 vdosys0 clock support") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220816193257.658487-2-nfraprado@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-16clk: mediatek: reset: Add infra_ao reset support for MT8186Rex-BC Chen1-0/+23
The infra_ao reset is needed for MT8186. - Add mtk_clk_rst_desc for MT8186. - Add register reset controller function for MT8186 infra_ao. - Add infra_ao_idx_map for MT8186. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-20-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-16clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195Rex-BC Chen4-6/+60
The infra_ao reset is needed for MT8192 and MT8195. - Add mtk_clk_rst_desc for MT8192 and MT8195 - Add register reset controller function for MT8192 infra_ao. - Move definition of infra reset from cl-mt8183.c to reset.h because it's the same definition with MT8192 and MT8195. - Add new definition of infra reset_4 for MT8192 and MT8195. - Add infra_ao_idx_map for MT8192 and MT8195. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> [Nícolas: Test for MT8192] Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-15-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-16clk: mediatek: reset: Add reset support for simple probeRex-BC Chen2-0/+8
- Add a pointer of "mtk_clk_rst_desc" to "mtk_clk_desc". - Add register reset with device function in mtk_clk_simple_probe(). Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-12-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-16clk: mediatek: reset: Add new register reset function with deviceRex-BC Chen13-16/+86
Using device to register reset controller is a better implementation in current drivers. Howerver, some clock drviers of MediaTek only provide device_node. Therefore, we still remain the register reset function with device_node and add a new function with device to register reset controller. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-11-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-16clk: mediatek: reset: Change return type for clock reset register functionRex-BC Chen2-8/+13
To deal with error handling, we change the function return type from void to int for mtk_clk_register_rst_ctrl(). Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-10-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-16clk: mediatek: reset: Support inuput argument index modeRex-BC Chen2-1/+25
There is a large number of mediatek infra reset bits, but we do not use all of them. In addition, the proper input argement of reset controller soulde be index. Therefore, to be compatible with previous drivers and usage, we add description variables to store the ids which can mapping to index. To use this mode, we need to put the id in rst_idx_map to map from index to ids. For example, if we want to input index 1 (this index is used to set bank 1 bit 14) for svs, we need to declare the reset controller like this: In drivers: static u16 rst_ofs[] = { 0x120, 0x130, 0x140, 0x150, 0x730, }; static u16 rst_idx_map[] = { 0 * 32 + 0, 1 * 32 + 14, .... }; static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SET_CLR, .rst_bank_ofs = rst_ofs, .rst_bank_nr = ARRAY_SIZE(rst_ofs), .rst_idx_map = rst_idx_map, .rst_idx_map_nr = ARRAY_SIZE(rst_idx_map), }; In dts: svs: { ... resets = <&infra 1>; ... }; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-9-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-16clk: mediatek: reset: Support nonsequence base offsets of reset registersRex-BC Chen15-43/+85
The bank offsets are not serial for all reset registers. For example, there are five infra reset banks for MT8192: 0x120, 0x130, 0x140, 0x150 and 0x730. To support this, - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of the reset register. - Add a new define RST_NR_PER_BANK to define reset number for each reset bank. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-8-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-16clk: mediatek: reset: Revise structure to control reset registerRex-BC Chen15-40/+186
To declare the reset data easier, we add a strucure to do this instead of using many input variables to mtk_register_reset_controller(). - Add mtk_clk_rst_desc to define the reset description when registering the reset controller. - Rename "mtk_reset" to "mtk_clk_rst_data". We use it to store data of reset controller. - Document mtk_clk_rst_desc and mtk_clk_rst_data. - Modify the documentation of mtk_register_reset_controller. - Extract container_of in update functions to to_mtk_clk_rst_data(). Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-7-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-16clk: mediatek: reset: Merge and revise reset register functionRex-BC Chen15-46/+61
There are two versions for clock reset register control for MediaTek SoCs. The old hardware is one bit per reset control, and does not have separate registers for bit set, clear and read-back operations. This matches the scheme supported by the simple reset driver. However, because we need to use different data structure from reset_simple_data, we can not use the operation of simple reset driver. For this reason, we keep the original functions and name this version as "MTK_RST_SIMPLE". In this patch: - Add a version enumeration to separate different reset hardware. - Merge the reset register function of simple and set_clr into one function "mtk_register_reset_controller". - Rename input variable "num_regs" to "rst_bank_nr" to avoid confusion. This variable is used to define the quantity of reset bank. - Document mtk_reset_version and mtk_register_reset_controller. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-6-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-16clk: mediatek: reset: Extract common drivers to update functionRex-BC Chen1-16/+22
To make drivers more clear and readable, we extract common code within assert and deassert to mtk_reset_update_set_clr() and mtk_reset_update(). Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-5-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-16clk: mediatek: reset: Refine and reorder functions in reset.cRex-BC Chen1-32/+36
To make drivers more readable, we modify the indentation of the drivers and reorder the location of functions. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-4-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-16clk: mediatek: reset: Fix written reset bit offsetRex-BC Chen1-2/+2
Original assert/deassert bit is BIT(0), but it's more resonable to modify them to BIT(id % 32) which is based on id. This patch will not influence any previous driver because the reset is only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0. Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver") Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-3-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-24 23:25:26 +0300