index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
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path:
root
/
drivers
/
clk
/
ingenic
Age
Commit message (
Expand
)
Author
Files
Lines
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
Thomas Gleixner
4
-40
/
+4
2019-05-21
treewide: Add SPDX license identifier - Makefile/Kconfig
Thomas Gleixner
2
-0
/
+2
2019-05-15
clk: Remove io.h from clk-provider.h
Stephen Boyd
4
-0
/
+4
2019-04-11
clk: ingenic: jz4725b: Add UDC PHY clock
Paul Cercueil
1
-0
/
+6
2019-02-26
clk: ingenic: Remove set but not used variable 'enable'
YueHaibing
1
-2
/
+1
2019-02-22
clk: ingenic: Fix doc of ingenic_cgu_div_info
Paul Cercueil
1
-1
/
+1
2019-02-22
clk: ingenic: Fix round_rate misbehaving with non-integer dividers
Paul Cercueil
1
-5
/
+5
2019-02-06
clk: ingenic: jz4740: Fix gating of UDC clock
Paul Cercueil
1
-1
/
+1
2018-10-17
clk: Add Ingenic jz4725b CGU driver
Paul Cercueil
3
-0
/
+236
2018-10-17
clk: ingenic: Add proper Kconfig entries
Paul Cercueil
2
-4
/
+41
2018-07-06
clk: ingenic: Add missing flag for UDC clock
Paul Cercueil
1
-1
/
+1
2018-07-06
clk: ingenic: Fix incorrect data for the i2s clock
Paul Cercueil
1
-1
/
+1
2018-06-16
docs: Fix some broken references
Mauro Carvalho Chehab
1
-1
/
+1
2018-06-02
clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
Paul Cercueil
1
-1
/
+1
2018-06-02
clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
Paul Cercueil
1
-2
/
+2
2018-06-02
clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle
Paul Cercueil
1
-1
/
+2
2018-06-02
clk: ingenic: jz4770: Change OTG from custom to standard gated clock
Paul Cercueil
1
-37
/
+5
2018-06-02
clk: ingenic: Support specifying "wait for clock stable" delay
Paul Cercueil
2
-0
/
+5
2018-06-02
clk: ingenic: Add support for clocks whose gate bit is inverted
Paul Cercueil
2
-2
/
+5
2018-01-19
clk: Add Ingenic jz4770 CGU driver
Paul Cercueil
2
-0
/
+484
2018-01-19
clk: ingenic: Add code to enable/disable PLLs
Paul Cercueil
1
-15
/
+74
2018-01-19
clk: ingenic: support PLLs with no bypass bit
Paul Cercueil
2
-1
/
+4
2018-01-19
clk: ingenic: Fix recalc_rate for clocks with fixed divider
Paul Cercueil
1
-0
/
+2
2018-01-19
clk: ingenic: Use const pointer to clk_ops in struct
Paul Cercueil
2
-2
/
+2
2017-11-03
Update MIPS email addresses
Paul Burton
4
-4
/
+4
2016-05-13
clk: ingenic: Allow divider value to be divided
Harvey Hunt
4
-34
/
+47
2015-07-20
clk: ingenic: Include clk.h
Stephen Boyd
1
-0
/
+1
2015-06-21
clk: ingenic: add JZ4780 CGU support
Paul Burton
2
-0
/
+734
2015-06-21
MIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cgu
Paul Burton
1
-0
/
+37
2015-06-21
MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cgu
Paul Burton
1
-0
/
+22
2015-06-21
MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu
Paul Burton
1
-0
/
+22
2015-06-21
MIPS,clk: migrate JZ4740 to common clock framework
Paul Burton
2
-0
/
+223
2015-06-21
clk: ingenic: add driver for Ingenic SoC CGU clocks
Paul Burton
3
-0
/
+935