| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-11-01 | clk: hi6220: mark clock cs_atb_syspll as critical | Leo Yan | 1 | -1/+1 |
| 2017-09-01 | clk: hi6220: change watchdog clock source | Leo Yan | 1 | -3/+3 |
| 2017-06-20 | clk: hi6220: add acpu clock | Zhangfei Gao | 1 | -0/+22 |
| 2017-04-12 | clk: hi6220: add debug APB clock | Leo Yan | 1 | -0/+1 |
| 2016-10-18 | clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init | Shawn Guo | 1 | -2/+2 |
| 2016-07-07 | clk: hi6220: Change syspll and media_syspll clk to 1.19GHz | Xinliang Liu | 1 | -2/+2 |
| 2016-06-30 | clk: hi6220: Add RTC clock for pl031 | Zhangfei Gao | 1 | -0/+2 |
| 2016-03-03 | clk: hisilicon: Remove CLK_IS_ROOT | Stephen Boyd | 1 | -13/+13 |
| 2015-06-04 | clk: hi6220: Clock driver support for Hisilicon hi6220 SoC | Bintian Wang | 1 | -0/+284 |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |