summaryrefslogtreecommitdiff
path: root/drivers/clk/clk-vt8500.c
AgeCommit message (Expand)AuthorFilesLines
2013-07-03Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds1-4/+71
2013-05-30clk: vt8500: Fix unbalanced spinlock in vt8500_dclk_set_rate()Tony Prisk1-1/+1
2013-05-30clk: vt8500: Remove unnecessary divisor adjustment in vtwm_dclk_set_rate()Tony Prisk1-4/+0
2013-05-30clk: vt8500: Add support for clocks on the WM8850 SoCsTony Prisk1-0/+71
2013-04-30Merge tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds1-0/+2
2013-04-14clk: vt8500: Missing breaks in vtwm_pll_round_rate/_set_rate.Tony Prisk1-0/+2
2013-03-15clk: vt8500: Fix "fix device clock divisor calculations"Arnd Bergmann1-1/+1
2013-01-24clk: vt8500: Use common of_clk_init() functionPrashant Gaikwad1-12/+5
2013-01-16clk: vt8500: Add support for WM8750/WM8850 PLL clocksTony Prisk1-2/+100
2013-01-16clk: vt8500: Fix division-by-0 when requested rate=0Tony Prisk1-2/+12
2013-01-16clk: vt8500: Fix device clock divisor calculationsTony Prisk1-0/+8
2013-01-16clk: vt8500: Fix error in PLL calculations on non-exact match.Tony Prisk1-3/+3
2012-11-10CLK: vt8500: Fix SDMMC clk special casesTony Prisk1-0/+18
2012-09-21arm: vt8500: clk: Add Common Clock Framework supportTony Prisk1-0/+510
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-16 01:05:35 +0300