index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
clk-vt8500.c
Age
Commit message (
Expand
)
Author
Files
Lines
2013-09-29
ARM: vt8500: prepare for arch-wide .init_time callback
Sebastian Hesselbarth
1
-10
/
+0
2013-09-29
clk: vt8500: parse pmc_base from clock driver
Sebastian Hesselbarth
1
-0
/
+24
2013-07-03
Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux
Linus Torvalds
1
-4
/
+71
2013-05-30
clk: vt8500: Fix unbalanced spinlock in vt8500_dclk_set_rate()
Tony Prisk
1
-1
/
+1
2013-05-30
clk: vt8500: Remove unnecessary divisor adjustment in vtwm_dclk_set_rate()
Tony Prisk
1
-4
/
+0
2013-05-30
clk: vt8500: Add support for clocks on the WM8850 SoCs
Tony Prisk
1
-0
/
+71
2013-04-30
Merge tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linux
Linus Torvalds
1
-0
/
+2
2013-04-14
clk: vt8500: Missing breaks in vtwm_pll_round_rate/_set_rate.
Tony Prisk
1
-0
/
+2
2013-03-15
clk: vt8500: Fix "fix device clock divisor calculations"
Arnd Bergmann
1
-1
/
+1
2013-01-24
clk: vt8500: Use common of_clk_init() function
Prashant Gaikwad
1
-12
/
+5
2013-01-16
clk: vt8500: Add support for WM8750/WM8850 PLL clocks
Tony Prisk
1
-2
/
+100
2013-01-16
clk: vt8500: Fix division-by-0 when requested rate=0
Tony Prisk
1
-2
/
+12
2013-01-16
clk: vt8500: Fix device clock divisor calculations
Tony Prisk
1
-0
/
+8
2013-01-16
clk: vt8500: Fix error in PLL calculations on non-exact match.
Tony Prisk
1
-3
/
+3
2012-11-10
CLK: vt8500: Fix SDMMC clk special cases
Tony Prisk
1
-0
/
+18
2012-09-21
arm: vt8500: clk: Add Common Clock Framework support
Tony Prisk
1
-0
/
+510