index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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tree
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log msg
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path:
root
/
drivers
/
clk
/
clk-versaclock5.c
Age
Commit message (
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)
Author
Files
Lines
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
Thomas Gleixner
1
-10
/
+1
2019-01-09
clk: vc5: Abort clock configuration without upstream clock
Marek Vasut
1
-1
/
+3
2018-12-15
clk: vc5: Add suspend/resume support
Marek Vasut
1
-0
/
+25
2017-07-17
clk: vc5: Add support for IDT VersaClock 5P49V5925
Vladimir Barinov
1
-0
/
+11
2017-07-17
clk: vc5: Add support for IDT VersaClock 5P49V6901
Marek Vasut
1
-0
/
+11
2017-07-17
clk: vc5: Add support for the input frequency doubler
Marek Vasut
1
-1
/
+77
2017-07-17
clk: vc5: Split clock input mux and predivider
Marek Vasut
1
-12
/
+34
2017-07-17
clk: vc5: Configure the output buffer input mux on prepare
Marek Vasut
1
-0
/
+19
2017-07-17
clk: vc5: Do not warn about disabled output buffer input muxes
Marek Vasut
1
-0
/
+3
2017-07-17
clk: vc5: Fix trivial typo
Marek Vasut
1
-1
/
+1
2017-07-17
clk: vc5: Prevent division by zero on unconfigured outputs
Marek Vasut
1
-0
/
+4
2017-04-19
clk: vc5: Add support for IDT VersaClock 5P49V5935
Alexey Firago
1
-2
/
+13
2017-04-19
clk: vc5: Add structure to describe particular chip features
Alexey Firago
1
-18
/
+47
2017-01-21
clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933
Marek Vasut
1
-0
/
+791