index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
clk-versaclock5.c
Age
Commit message (
Expand
)
Author
Files
Lines
2022-11-23
clk: Remove a useless include
Christophe JAILLET
1
-1
/
+0
2022-10-08
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
1
-58
/
+105
2022-10-04
Merge branches 'clk-baikal', 'clk-broadcom', 'clk-vc5' and 'clk-versaclock' i...
Stephen Boyd
1
-57
/
+104
2022-10-03
clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975
Matthias Fend
1
-0
/
+11
2022-10-01
clk: vc5: Use regmap_{set,clear}_bits() where appropriate
Lars-Peter Clausen
1
-20
/
+15
2022-10-01
clk: vc5: Check IO access results
Lars-Peter Clausen
1
-50
/
+91
2022-10-01
clk: vc5: Fix 5P49V6901 outputs disabling when enabling FOD
Serge Semin
1
-1
/
+1
2022-08-23
dt-bindings: clock: Move versaclock.h to dt-bindings/clock
Lukas Bulwahn
1
-1
/
+1
2022-08-16
i2c: Make remove callback return void
Uwe Kleine-König
1
-3
/
+1
2021-11-03
clk: vc5: Use i2c .probe_new
Luca Ceresoli
1
-2
/
+2
2021-08-29
clk: vc5: Add properties for configuring SD/OE behavior
Sean Anderson
1
-0
/
+24
2021-08-29
clk: vc5: Use dev_err_probe
Sean Anderson
1
-10
/
+10
2021-06-09
clk: vc5: fix output disabling when enabling a FOD
Luca Ceresoli
1
-3
/
+24
2021-02-11
clk: vc5: Add support for optional load capacitance
Adam Ford
1
-0
/
+64
2020-12-20
clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"
Geert Uytterhoeven
1
-2
/
+2
2020-07-24
clk: vc5: use a dedicated struct to describe the output drivers
Luca Ceresoli
1
-9
/
+15
2020-07-23
clk: vc5: Add memory check to prevent oops
Adam Ford
1
-3
/
+5
2020-07-23
clk: vc5: fix use of memory after it has been kfree'd
Colin Ian King
1
-32
/
+18
2020-06-23
clk: vc5: Enable addition output configurations of the Versaclock
Adam Ford
1
-0
/
+156
2020-06-23
clk: vc5: Allow Versaclock driver to support multiple instances
Adam Ford
1
-47
/
+37
2020-05-30
clk: vc5: Add support for IDT VersaClock 5P49V6965
Adam Ford
1
-0
/
+11
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
Thomas Gleixner
1
-10
/
+1
2019-01-09
clk: vc5: Abort clock configuration without upstream clock
Marek Vasut
1
-1
/
+3
2018-12-15
clk: vc5: Add suspend/resume support
Marek Vasut
1
-0
/
+25
2017-07-17
clk: vc5: Add support for IDT VersaClock 5P49V5925
Vladimir Barinov
1
-0
/
+11
2017-07-17
clk: vc5: Add support for IDT VersaClock 5P49V6901
Marek Vasut
1
-0
/
+11
2017-07-17
clk: vc5: Add support for the input frequency doubler
Marek Vasut
1
-1
/
+77
2017-07-17
clk: vc5: Split clock input mux and predivider
Marek Vasut
1
-12
/
+34
2017-07-17
clk: vc5: Configure the output buffer input mux on prepare
Marek Vasut
1
-0
/
+19
2017-07-17
clk: vc5: Do not warn about disabled output buffer input muxes
Marek Vasut
1
-0
/
+3
2017-07-17
clk: vc5: Fix trivial typo
Marek Vasut
1
-1
/
+1
2017-07-17
clk: vc5: Prevent division by zero on unconfigured outputs
Marek Vasut
1
-0
/
+4
2017-04-19
clk: vc5: Add support for IDT VersaClock 5P49V5935
Alexey Firago
1
-2
/
+13
2017-04-19
clk: vc5: Add structure to describe particular chip features
Alexey Firago
1
-18
/
+47
2017-01-21
clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933
Marek Vasut
1
-0
/
+791