starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Collapse)	Author	Files	Lines
2018-08-30	clk: Convert to using %pOFn instead of device_node.name	Rob Herring	1	-2/+2
	In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-omap@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2017-11-14	ARC: clk: fix spelling mistake: "configurarion" -> "configuration"	Colin Ian King	1	-2/+2
	Trivial fix to spelling mistake in dev_dbg message Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31	ARC: clk: introduce HSDK pll driver	Eugeniy Paltsev	1	-0/+431
	HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi. By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>