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path: root/drivers/clk/clk-composite.c
AgeCommit message (Expand)AuthorFilesLines
2018-12-11clk: Tag basic clk types with SPDXStephen Boyd1-12/+1
2016-04-22Merge branch 'clk-hw-register' (early part) into clk-nextStephen Boyd1-12/+33
2016-04-22Merge branch 'clk-composite-unregister' into clk-nextStephen Boyd1-0/+15
2016-04-22clk: composite: Add unregister functionMaxime Ripard1-0/+15
2016-04-20clk: composite: Add hw based registration APIsStephen Boyd1-12/+33
2016-04-16clk: Add clk_composite_set_rate_and_parentFinley Xiao1-0/+33
2016-01-29clk: move the common clock's to_clk_*(_hw) macros to clk-provider.hGeliang Tang1-2/+0
2015-08-25clk: Convert basic types to clk_hw based provider APIsStephen Boyd1-7/+7
2015-08-25clk: Convert __clk_get_flags() to clk_hw_get_flags()Stephen Boyd1-1/+1
2015-08-25clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()Stephen Boyd1-1/+1
2015-07-28clk: fix some determine_rate implementationsBoris Brezillon1-2/+1
2015-07-28clk: change clk_ops' ->determine_rate() prototypeBoris Brezillon1-24/+24
2015-05-15clk: basic-types: Remove useless allocation failure printksStephen Boyd1-3/+1
2015-05-06clk: make strings in parent name arrays constSascha Hauer1-1/+1
2015-02-18clk: Replace explicit clk assignment with __clk_hw_set_clkJavier Martinez Canillas1-10/+10
2015-02-03clk: Add rate constraints to clocksTomeu Vizoso1-2/+7
2014-12-04clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso1-4/+5
2014-07-13clk: composite: improve rate_hw sanity check logicMike Turquette1-10/+16
2014-07-13clk: composite: allow read-only clocksHeiko Stübner1-6/+3
2014-07-13clk: composite: support determine_rate using rate_ops->round_rate + mux_ops->...Boris BREZILLON1-1/+47
2014-01-15clk: composite: pass mux_hw into determine_rateMike Turquette1-1/+1
2013-11-10clk: composite: .determine_rate supportEmilio López1-0/+28
2013-04-12clk: composite: allow fixed rates & fixed dividersMike Turquette1-4/+13
2013-04-12clk: composite: rename 'div' references to 'rate'Mike Turquette1-20/+20
2013-03-26clk: Add composite clock typePrashant Gaikwad1-0/+201