index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
clk-aspeed.c
Age
Commit message (
Expand
)
Author
Files
Lines
2018-07-11
clk: aspeed: Support HPLL strapping on ast2400
Joel Stanley
1
-13
/
+29
2018-07-06
clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as critical
Joel Stanley
1
-2
/
+2
2018-07-06
clk: aspeed: Treat a gate in reset as disabled
Benjamin Herrenschmidt
1
-0
/
+13
2018-06-09
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
1
-11
/
+46
2018-06-06
treewide: Use struct_size() for kmalloc()-family
Kees Cook
1
-3
/
+3
2018-06-04
Merge branches 'clk-imx6sx', 'clk-imx7d-enet' and 'clk-aspeed-24' into clk-next
Stephen Boyd
1
-1
/
+8
2018-06-01
clk: aspeed: Add 24MHz fixed clock
Lei YU
1
-1
/
+8
2018-05-16
clk:aspeed: Fix reset bits for PCI/VGA and PECI
Jae Hyun Yoo
1
-2
/
+2
2018-05-16
clk: aspeed: Support second reset register
Joel Stanley
1
-8
/
+36
2018-03-15
clk: aspeed: Prevent reset if clock is enabled
Eddie James
1
-12
/
+17
2018-03-15
clk: aspeed: Fix is_enabled for certain clocks
Eddie James
1
-1
/
+2
2018-01-27
clk: aspeed: Handle inverse polarity of USB port 1 clock gate
Benjamin Herrenschmidt
1
-3
/
+12
2018-01-27
clk: aspeed: Fix return value check in aspeed_cc_init()
Wei Yongjun
1
-1
/
+1
2018-01-27
clk: aspeed: Add reset controller
Joel Stanley
1
-1
/
+81
2018-01-27
clk: aspeed: Register gated clocks
Joel Stanley
1
-0
/
+130
2018-01-27
clk: aspeed: Add platform driver and register PLLs
Joel Stanley
1
-0
/
+130
2018-01-27
clk: aspeed: Register core clocks
Joel Stanley
1
-0
/
+177
2018-01-27
clk: Add clock driver for ASPEED BMC SoCs
Joel Stanley
1
-0
/
+141