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path: root/drivers/clk/bcm/clk-bcm2835.c
AgeCommit message (Expand)AuthorFilesLines
2017-01-21clk: bcm2835: Add leaf clock measurement support, disabled by defaultEric Anholt1-25/+119
2017-01-21clk: bcm2835: Register the DSI0/DSI1 pixel clocks.Eric Anholt1-12/+109
2017-01-21clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.Eric Anholt1-14/+28
2016-12-12clk: bcm: Fix 'maybe-uninitialized' warning in bcm2835_clock_choose_div_and_p...Boris Brezillon1-1/+1
2016-12-09clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clockBoris Brezillon1-1/+6
2016-12-09clk: bcm: Support rate change propagation on bcm2835 clocksBoris Brezillon1-4/+63
2016-12-09clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clkBoris Brezillon1-1/+3
2016-11-23clk: bcm2835: Fix ->fixed_divider of pllh_auxBoris Brezillon1-1/+1
2016-10-18clk: bcm2835: Clamp the PLL's requested rate to the hardware limits.Eric Anholt1-7/+4
2016-09-15clk: bcm2835: Migrate to clk_hw based registration and OF APIsStephen Boyd1-39/+46
2016-09-07clk: bcm2835: Skip PLLC clocks when deciding on a new clock parentEric Anholt1-0/+23
2016-09-07clk: bcm2835: Mark the CM SDRAM clock's parent as criticalEric Anholt1-0/+25
2016-09-07clk: bcm2835: Mark GPIO clocks enabled at boot as criticalEric Anholt1-1/+9
2016-09-07clk: bcm2835: Mark the VPU clock as criticalEric Anholt1-1/+4
2016-04-20clk: bcm2835: Fix PLL poweronEric Anholt1-0/+4
2016-04-20clk: bcm2835: Fix compiler warnings on 64-bit buildsEric Anholt1-4/+4
2016-03-17clk: bcm2835: add missing osc and per clocksMartin Sperl1-0/+90
2016-03-17clk: bcm2835: add missing PLL clock dividersMartin Sperl1-0/+32
2016-03-17clk: bcm2835: enable management of PCM clockMartin Sperl1-0/+7
2016-03-17clk: bcm2835: reorganize bcm2835_clock_array assignmentMartin Sperl1-459/+393
2016-03-17clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in driverMartin Sperl1-73/+94
2016-03-17clk: bcm2835: expose raw clock-registers via debugfsMartin Sperl1-0/+101
2016-03-17clk: bcm2835: clean up coding style issuesMartin Sperl1-6/+2
2016-03-17clk: bcm2835: correctly enable fractional clock supportMartin Sperl1-6/+39
2016-03-17clk: bcm2835: divider value has to be 1 or moreMartin Sperl1-2/+3
2016-03-17clk: bcm2835: add locking to pll*_on/off methodsMartin Sperl1-0/+4
2016-03-17clk: bcm2835: pll_off should only update CM_PLL_ANARSTMartin Sperl1-2/+8
2016-03-03clk: bcm: Remove CLK_IS_ROOTStephen Boyd1-6/+3
2016-02-26clk: bcm2835: added missing clock register definitionsMartin Sperl1-0/+13
2016-02-16clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate()Eric Anholt1-11/+2
2016-02-16clk: bcm2835: Fix setting of PLL divider clock ratesEric Anholt1-5/+7
2015-12-25clk: bcm2835: Add PWM clock supportRemi Pommarel1-0/+13
2015-12-25clk: bcm2835: Support for clock parent selectionRemi Pommarel1-45/+77
2015-12-25clk: bcm2835: add a round up ability to the clock divisorRemi Pommarel1-10/+12
2015-10-12clk: bcm2835: Add support for programming the audio domain clocksEric Anholt1-1/+1521
2015-10-02clk: bcm2835: Move under bcm/ with other Broadcom SoC clk drivers.Eric Anholt1-0/+55