index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
clk
/
actions
Age
Commit message (
Expand
)
Author
Files
Lines
2019-05-21
treewide: Add SPDX license identifier - Makefile/Kconfig
Thomas Gleixner
2
-0
/
+2
2019-05-01
clk: actions: Use the correct style for SPDX License Identifier
Nishad Kamdar
9
-9
/
+9
2019-02-22
clk: actions: Add clock driver for S500 SoC
Manivannan Sadhasivam
3
-0
/
+531
2019-02-22
clk: actions: Add configurable PLL delay
Manivannan Sadhasivam
2
-7
/
+25
2018-10-17
clk: actions: Add Actions Semi S900 SoC Reset Management Unit support
Manivannan Sadhasivam
1
-0
/
+82
2018-10-17
clk: actions: Add Actions Semi S700 SoC Reset Management Unit support
Manivannan Sadhasivam
1
-0
/
+51
2018-10-17
clk: actions: Add Actions Semi Owl SoCs Reset Management Unit support
Manivannan Sadhasivam
5
-0
/
+101
2018-10-17
clk: actions: Cache regmap info in private clock descriptor
Manivannan Sadhasivam
4
-6
/
+8
2018-07-26
clk: actions: Add S700 SoC clock support
Saravanan Sekar
3
-0
/
+613
2018-07-26
clk: actions: Add missing REGMAP_MMIO dependency
Saravanan Sekar
1
-0
/
+1
2018-04-07
clk: actions: Add S900 SoC clock support
Manivannan Sadhasivam
3
-0
/
+734
2018-04-07
clk: actions: Add pll clock support
Manivannan Sadhasivam
3
-0
/
+287
2018-04-07
clk: actions: Add composite clock support
Manivannan Sadhasivam
3
-0
/
+324
2018-04-07
clk: actions: Add fixed factor clock support
Manivannan Sadhasivam
1
-0
/
+28
2018-04-07
clk: actions: Add factor clock support
Manivannan Sadhasivam
3
-0
/
+306
2018-04-07
clk: actions: Add divider clock support
Manivannan Sadhasivam
3
-0
/
+170
2018-04-07
clk: actions: Add mux clock support
Manivannan Sadhasivam
3
-0
/
+122
2018-04-07
clk: actions: Add gate clock support
Manivannan Sadhasivam
3
-0
/
+151
2018-04-07
clk: actions: Add common clock driver support
Manivannan Sadhasivam
4
-0
/
+137