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2025-04-26Merge tag 'for-linus' of https://github.com/openrisc/linuxLinus Torvalds8-75/+196
Pull OpenRISC updates from Stafford Horne: - Support for cacheinfo API to expose OpenRISC cache info via sysfs, this also translated to some cleanups to OpenRISC cache flush and invalidate API's - Documentation updates for new mailing list and toolchain binaries * tag 'for-linus' of https://github.com/openrisc/linux: Documentation: openrisc: Update toolchain binaries URL Documentation: openrisc: Update mailing list openrisc: Add cacheinfo support openrisc: Introduce new utility functions to flush and invalidate caches openrisc: Refactor struct cpuinfo_or1k to reduce duplication
2025-04-26crypto: arm64/sha1 - Set finalize for short finupHerbert Xu1-1/+3
Always set sctx->finalize before calling finup as it may not have been set previously on a short final. Reported-by: Corentin LABBE <clabbe.montjoie@gmail.com> Fixes: b97d31100e36 ("crypto: arm64/sha1 - Use API partial block handling") Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Tested-by: Corentin LABBE <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-26crypto: arm/blake2b - Set FINAL_NONZEROHerbert Xu1-1/+2
Set FINAL_NONZERO as blake2b expects to have at least one byte for finalisation. Reported-by: Corentin LABBE <clabbe.montjoie@gmail.com> Fixes: cc28260ab4fb ("crypto: arm/blake2b - Use API partial block handling") Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Tested-by: Corentin LABBE <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-26platform/x86/amd/pmc: Use FCH_PM_BASE definitionMario Limonciello1-0/+1
The s2idle MMIO quirk uses a scratch register in the FCH. Adjust the code to clarify that. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Cc: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Cc: Yazen Ghannam <yazen.ghannam@amd.com> Cc: platform-driver-x86@vger.kernel.org Link: https://lore.kernel.org/r/20250422234830.2840784-5-superm1@kernel.org
2025-04-26i2c: piix4, x86/platform: Move the SB800 PIIX4 FCH definitions to ↵Mario Limonciello1-0/+11
<asm/amd/fch.h> SB800_PIIX4_FCH_PM_ADDR is used to indicate the base address for the FCH PM registers. Multiple drivers may need this base address, so move related defines to a common header location and rename them accordingly. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Acked-by: Andi Shyti <andi.shyti@kernel.org> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Cc: Jean Delvare <jdelvare@suse.com> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Sanket Goswami <Sanket.Goswami@amd.com> Cc: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Cc: Yazen Ghannam <yazen.ghannam@amd.com> Cc: linux-i2c@vger.kernel.org Link: https://lore.kernel.org/r/20250422234830.2840784-4-superm1@kernel.org
2025-04-26LoongArch: KVM: Fix PMU pass-through issue if VM exits to host finallyBibo Mao1-0/+1
In function kvm_pre_enter_guest(), it prepares to enter guest and check whether there are pending signals or events. And it will not enter guest if there are, PMU pass-through preparation for guest should be cancelled and host should own PMU hardware. Cc: stable@vger.kernel.org Fixes: f4e40ea9f78f ("LoongArch: KVM: Add PMU support for guest") Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-04-26LoongArch: KVM: Fully clear some CSRs when VM rebootBibo Mao1-0/+7
Some registers such as LOONGARCH_CSR_ESTAT and LOONGARCH_CSR_GINTC are partly cleared with function _kvm_setcsr(). This comes from the hardware specification, some bits are read only in VM mode, and however they can be written in host mode. So they are partly cleared in VM mode, and can be fully cleared in host mode. These read only bits show pending interrupt or exception status. When VM reset, the read-only bits should be cleared, otherwise vCPU will receive unknown interrupts in boot stage. Here registers LOONGARCH_CSR_ESTAT/LOONGARCH_CSR_GINTC are fully cleared in ioctl KVM_REG_LOONGARCH_VCPU_RESET vCPU reset path. Cc: stable@vger.kernel.org Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-04-26LoongArch: KVM: Fix multiple typos of KVM codeYulong Han2-4/+4
Fix multiple typos inside arch/loongarch/kvm. Cc: stable@vger.kernel.org Reviewed-by: Yuli Wang <wangyuli@uniontech.com> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Yulong Han <wheatfox17@icloud.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-04-26LoongArch: Return NULL from huge_pte_offset() for invalid PMDMing Wang1-1/+1
LoongArch's huge_pte_offset() currently returns a pointer to a PMD slot even if the underlying entry points to invalid_pte_table (indicating no mapping). Callers like smaps_hugetlb_range() fetch this invalid entry value (the address of invalid_pte_table) via this pointer. The generic is_swap_pte() check then incorrectly identifies this address as a swap entry on LoongArch, because it satisfies the "!pte_present() && !pte_none()" conditions. This misinterpretation, combined with a coincidental match by is_migration_entry() on the address bits, leads to kernel crashes in pfn_swap_entry_to_page(). Fix this at the architecture level by modifying huge_pte_offset() to check the PMD entry's content using pmd_none() before returning. If the entry is invalid (i.e., it points to invalid_pte_table), return NULL instead of the pointer to the slot. Cc: stable@vger.kernel.org Acked-by: Peter Xu <peterx@redhat.com> Co-developed-by: Hongchen Zhang <zhanghongchen@loongson.cn> Signed-off-by: Hongchen Zhang <zhanghongchen@loongson.cn> Signed-off-by: Ming Wang <wangming01@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-04-26LoongArch: Remove a bogus reference to ZONE_DMAPetr Tesarik1-3/+0
Remove dead code. LoongArch does not have a DMA memory zone (24bit DMA). The architecture does not even define MAX_DMA_PFN. Cc: stable@vger.kernel.org Reviewed-by: Mike Rapoport (Microsoft) <rppt@kernel.org> Signed-off-by: Petr Tesarik <ptesarik@suse.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-04-26LoongArch: Handle fp, lsx, lasx and lbt assembly symbolsTiezhu Yang5-40/+40
Like the other relevant symbols, export some fp, lsx, lasx and lbt assembly symbols and put the function declarations in header files rather than source files. While at it, use "asmlinkage" for the other existing C prototypes of assembly functions and also do not use the "extern" keyword with function declarations according to the document coding-style.rst. Cc: stable@vger.kernel.org # 6.6+ Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-04-26LoongArch: Make do_xyz() exception handlers more robustTiezhu Yang1-8/+12
Currently, interrupts need to be disabled before single-step mode is set, it requires that CSR_PRMD_PIE be cleared in save_local_irqflag() which is called by setup_singlestep(), this is reasonable. But in the first kprobe breakpoint exception, if the irq is enabled at the beginning of do_bp(), it will not be disabled at the end of do_bp() due to the CSR_PRMD_PIE has been cleared in save_local_irqflag(). So for this case, it may corrupt exception context when restoring the exception after do_bp() in handle_bp(), this is not reasonable. In order to restore exception safely in handle_bp(), it needs to ensure the irq is disabled at the end of do_bp(), so just add a local variable to record the original interrupt status in the parent context, then use it as the check condition to enable and disable irq in do_bp(). While at it, do the similar thing for other do_xyz() exception handlers to make them more robust. Fixes: 6d4cc40fb5f5 ("LoongArch: Add kprobes support") Suggested-by: Jinyang He <hejinyang@loongson.cn> Suggested-by: Huacai Chen <chenhuacai@loongson.cn> Co-developed-by: Tianyang Zhang <zhangtianyang@loongson.cn> Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-04-26LoongArch: Make regs_irqs_disabled() more clearTiezhu Yang1-2/+2
In the current code, the definition of regs_irqs_disabled() is actually "!(regs->csr_prmd & CSR_CRMD_IE)" because arch_irqs_disabled_flags() is defined as "!(flags & CSR_CRMD_IE)", it looks a little strange. Define regs_irqs_disabled() as !(regs->csr_prmd & CSR_PRMD_PIE) directly to make it more clear, no functional change. While at it, the return value of regs_irqs_disabled() is true or false, so change its type to reflect that and also make it always inline. Fixes: 803b0fc5c3f2 ("LoongArch: Add process management") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-04-26LoongArch: Select ARCH_USE_MEMTESTYuli Wang1-0/+1
As of commit dce44566192e ("mm/memtest: add ARCH_USE_MEMTEST"), architectures must select ARCH_USE_MEMTESET to enable CONFIG_MEMTEST. Commit 628c3bb40e9a ("LoongArch: Add boot and setup routines") added support for early_memtest but did not select ARCH_USE_MEMTESET. Fixes: 628c3bb40e9a ("LoongArch: Add boot and setup routines") Tested-by: Erpeng Xu <xuerpeng@uniontech.com> Tested-by: Yuli Wang <wangyuli@uniontech.com> Signed-off-by: Yuli Wang <wangyuli@uniontech.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-04-26riscv: defconfig: spacemit: enable clock controller driver for SpacemiT K1Haylen Chu1-0/+2
Clock controller unit, or CCU, generates various clocks frequency for peripherals integrated in SpacemiT K1 SoC and is essential for normal operation. Let's enable it as built-in driver in defconfig. Signed-off-by: Haylen Chu <heylenay@4d2.org> Reviewed-by: Alex Elder <elder@riscstar.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-04-26KVM: SVM: avoid frequency indirect callsPeng Hao1-0/+4
When retpoline is enabled, indirect function calls introduce additional performance overhead. Avoid frequent indirect calls to VMGEXIT when SEV is enabled. Signed-off-by: Peng Hao <flyingpeng@tencent.com> Link: https://lore.kernel.org/r/20250306075425.66693-1-flyingpeng@tencent.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-04-26KVM: SEV: Configure "ALLOWED_SEV_FEATURES" VMCB FieldKim Phillips3-1/+13
AMD EPYC 5th generation processors have introduced a feature that allows the hypervisor to control the SEV_FEATURES that are set for, or by, a guest [1]. ALLOWED_SEV_FEATURES can be used by the hypervisor to enforce that SEV-ES and SEV-SNP guests cannot enable features that the hypervisor does not want to be enabled. Always enable ALLOWED_SEV_FEATURES. A VMRUN will fail if any non-reserved bits are 1 in SEV_FEATURES but are 0 in ALLOWED_SEV_FEATURES. Some SEV_FEATURES - currently PmcVirtualization and SecureAvic (see Appendix B, Table B-4) - require an opt-in via ALLOWED_SEV_FEATURES, i.e. are off-by-default, whereas all other features are effectively on-by-default, but still honor ALLOWED_SEV_FEATURES. [1] Section 15.36.20 "Allowed SEV Features", AMD64 Architecture Programmer's Manual, Pub. 24593 Rev. 3.42 - March 2024: https://bugzilla.kernel.org/attachment.cgi?id=306250 Co-developed-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Kishon Vijay Abraham I <kvijayab@amd.com> Reviewed-by: Pankaj Gupta <pankaj.gupta@amd.com> Signed-off-by: Kim Phillips <kim.phillips@amd.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/r/20250310201603.1217954-3-kim.phillips@amd.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-04-26x86/cpufeatures: Add "Allowed SEV Features" FeatureKishon Vijay Abraham I1-0/+1
Add CPU feature detection for "Allowed SEV Features" to allow the Hypervisor to enforce that SEV-ES and SEV-SNP guest VMs cannot enable features (via SEV_FEATURES) that the Hypervisor does not support or wish to be enabled. Signed-off-by: Kishon Vijay Abraham I <kvijayab@amd.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Pankaj Gupta <pankaj.gupta@amd.com> Acked-by: Borislav Petkov (AMD) <bp@alien8.de> Signed-off-by: Kim Phillips <kim.phillips@amd.com> Link: https://lore.kernel.org/r/20250310201603.1217954-2-kim.phillips@amd.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-04-26KVM: SVM: Add a mutex to dump_vmcb() to prevent concurrent outputTom Lendacky1-0/+5
If multiple VMRUN instructions fail, resulting in calls to dump_vmcb(), the output can become interleaved and it is impossible to identify which line of output belongs to which VMCB. Add a mutex to dump_vmcb() so that the output is serialized. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Borislav Petkov (AMD) <bp@alien8.de> Tested-by: Kim Phillips <kim.phillips@amd.com> Link: https://lore.kernel.org/r/a880678afd9488e1dd6017445802712f7c02cc6d.1742477213.git.thomas.lendacky@amd.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-04-26KVM: SVM: Include the vCPU ID when dumping a VMCBTom Lendacky1-2/+2
Provide the vCPU ID of the VMCB in dump_vmcb(). Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Borislav Petkov (AMD) <bp@alien8.de> Tested-by: Kim Phillips <kim.phillips@amd.com> Link: https://lore.kernel.org/r/ee0af5a6c1a49aebb4a8291071c3f68cacf107b2.1742477213.git.thomas.lendacky@amd.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-04-26KVM: SVM: Add the type of VM for which the VMCB/VMSA is being dumpedTom Lendacky1-2/+7
Add the type of VM (SVM, SEV, SEV-ES, or SEV-SNP) being dumped to the dump_vmcb() function. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Borislav Petkov (AMD) <bp@alien8.de> Tested-by: Kim Phillips <kim.phillips@amd.com> Link: https://lore.kernel.org/r/7a183a8beedf4ee26c42001160e073a884fe466e.1742477213.git.thomas.lendacky@amd.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-04-26KVM: SVM: Dump guest register state in dump_vmcb()Tom Lendacky1-0/+53
Guest register state can be useful when debugging, include it as part of dump_vmcb(). Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Borislav Petkov (AMD) <bp@alien8.de> Tested-by: Kim Phillips <kim.phillips@amd.com> Link: https://lore.kernel.org/r/a4131a10c082a93610cac12b35dca90292e50f50.1742477213.git.thomas.lendacky@amd.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-04-26KVM: SVM: Decrypt SEV VMSA in dump_vmcb() if debugging is enabledTom Lendacky3-0/+122
An SEV-ES/SEV-SNP VM save area (VMSA) can be decrypted if the guest policy allows debugging. Update the dump_vmcb() routine to output some of the SEV VMSA contents if possible. This can be useful for debug purposes. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Borislav Petkov (AMD) <bp@alien8.de> Tested-by: Kim Phillips <kim.phillips@amd.com> Link: https://lore.kernel.org/r/ea3b852c295b6f4b200925ed6b6e2c90d9475e71.1742477213.git.thomas.lendacky@amd.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-04-25arm64: dts: ti: k3-am625-sk: Enable PWMJudith Mendez1-0/+40
PWM signals can be routed to the user expansion header on am625 SK and am62 lp sk. Enable eCAP0, eCAP1, eHRPWM1, and route the output PWM signals to pins on J3 header. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250422000851.4118545-4-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: dts: ti: k3-am62a7-sk: Enable PWMJudith Mendez1-0/+40
PWM signals can be routed to the user expansion header on am62a7 SK. Enable eCAP0, eCAP1, eHRPWM1, and route the output PWM signals to pins on J3 header. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250422000851.4118545-3-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: dts: ti: k3-am62p5-sk: Enable PWMJudith Mendez1-0/+54
PWM signals can be routed to the user expansion header on am62p5 SK. Enable eCAP0, eCAP1, eHRPWM0, eHRPWM1 and route the output PWM signals to pins on J4 header. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250422000851.4118545-2-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: dts: ti: Add basic support for phyBOARD-Izar-AM68xDominik Haller3-0/+1177
The phyCORE-AM68x/TDA4x [1] is a SoM (System on Module) featuring TI's AM68x/TDA4x SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM68x/TDA4x (J721S2) family. A reference carrier board design, called phyBOARD-Izar is used for the phyCORE-AM68x/TDA4x development kit [2]. Supported features: * Debug UART * 2x SPI NOR Flash * eMMC * 2x Ethernet * Micro SD card * I2C EEPROM * I2C RTC * 2x I2C GPIO Expander * LEDs * USB 5 Gbit/s * PCIe For more details see the product pages for the SoM and the development kit: [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/ [2] https://www.phytec.eu/en/produkte/development-kits/phyboard-izar/ Signed-off-by: Dominik Haller <d.haller@phytec.de> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Acked-by: Moteen Shah <m-shah@ti.com> Link: https://lore.kernel.org/r/20250423133635.29897-2-d.haller@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: defconfig: Enable TMP102 as moduleDominik Haller1-0/+1
Enable the driver for the TI TMP102 temperature sensors used on the Phytec phyCORE-AM68x/TDA4x and the phyGATE-Tauri-L-iMX8MM. Signed-off-by: Dominik Haller <d.haller@phytec.de> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250423133635.29897-3-d.haller@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: defconfig: Enable hwspinlock and eQEP for K3Judith Mendez1-0/+2
Enable CONFIG_HWSPINLOCK_OMAP to allow usage of these devices across K3 SoC's. Also enable CONFIG_TI_EQEP which is enabled by default on am64x SK board. Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20250421201055.3889680-1-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: defconfig: Add CDNS_DSI and CDNS_PHY configJayesh Choudhary1-0/+2
Enable configs for cdns-dsi and cdns-dphy drivers required for DSI display on the following platforms: J721E-EVM, J721E-BeagleBone-AI64, J721S2-EVM, AM68-SK, J722S-EVM, BeagleY-AI, AM62P5-SK, J784S4-EVM and J742S2-EVM The DSI wrapper driver used by all the above mentioned platforms, cdns-dsi-j721e is enabled by default if cdns-dsi config is enabled. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Judith Mendez <jm@ti.com> Link: https://lore.kernel.org/r/20250416182930.32132-1-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix length of serdes_ln_ctrlSiddharth Vadapalli1-1/+1
Commit under Fixes corrected the "mux-reg-masks" property but did not update the "length" field of the "reg" property to account for the newly added register offsets which extend the region. Fix this. Fixes: 38e7f9092efb ("arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix serdes_ln_ctrl reg-masks") Cc: stable@vger.kernel.org Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250423151612.48848-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: dts: ti: am65x: Add missing power-supply for Rocktech-rk101 panelAndrew Davis1-0/+12
Add the 5v0 supply that is provided over the display panel cable and used by the LCD. This is required by "simple panels" or we get the following warning from DTBS_CHECK: k3-am654-gp-evm.dtb: display0: 'power-supply' is a required property Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250421214620.3770172-4-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: dts: ti: k3-am65-main: Add system controller compatibleJan Kiszka1-1/+1
Now that the TI K3 AM654 system controller bindings also cover the usage in the main domain, add its compatible to address dtbs_check complains: k3-am654-base-board.dtb: scm-conf@100000: compatible: ['syscon', 'simple-mfd'] is too short Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250421214620.3770172-3-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: dts: ti: k3-j721e-common-proc-board-infotainment: Update to comply ↵Jayesh Choudhary2-25/+38
with device tree schema Fix hdmi-connector and tfp bridge node as per the bindings, - Remove 'digital' property which is required for DVI connector not HDMI - Add 'ti,deskew' property which is a required property - Fix ports property for tfp410 bridge - Change node names appropriately Redefine the ports for dss and for k3-j721e-common-proc-board.dts, add reg property for the port (@0) to get rid of dtbs_check warnings in infotainment overlay when ports for dss are re-defined. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250424080328.57671-1-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25Merge tag 'riscv-for-linus-6.15-rc4' of ↵Linus Torvalds2-13/+12
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Palmer Dabbelt: - A fix for a missing icache flush in uprobes, which manifests as at least a BFF selftest failure on the Spacemit X1 - A workaround for build warnings in flush_icache_range() * tag 'riscv-for-linus-6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: uprobes: Add missing fence.i after building the XOL buffer riscv: Replace function-like macro by static inline function
2025-04-25Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds11-83/+112
Pull kvm fixes from Paolo Bonzini: "ARM: - Single fix for broken usage of 'multi-MIDR' infrastructure in PI code, adding an open-coded erratum check for everyone's favorite pile of sand: Cavium ThunderX x86: - Bugfixes from a planned posted interrupt rework - Do not use kvm_rip_read() unconditionally to cater for guests with inaccessible register state" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: x86: Do not use kvm_rip_read() unconditionally for KVM_PROFILING KVM: x86: Do not use kvm_rip_read() unconditionally in KVM tracepoints KVM: SVM: WARN if an invalid posted interrupt IRTE entry is added iommu/amd: WARN if KVM attempts to set vCPU affinity without posted intrrupts iommu/amd: Return an error if vCPU affinity is set for non-vCPU IRTE KVM: x86: Take irqfds.lock when adding/deleting IRQ bypass producer KVM: x86: Explicitly treat routing entry type changes as changes KVM: x86: Reset IRTE to host control if *new* route isn't postable KVM: SVM: Allocate IR data using atomic allocation KVM: SVM: Don't update IRTEs if APICv/AVIC is disabled KVM: arm64, x86: make kvm_arch_has_irq_bypass() inline arm64: Rework checks for broken Cavium HW in the PI code
2025-04-25riscv: dts: thead: Introduce reset controller nodeMichal Wilczynski1-0/+6
T-HEAD TH1520 SoC requires to put the GPU out of the reset state as part of the power-up sequence. Link: https://lore.kernel.org/linux-riscv/81e53e3a-5873-44c7-9070-5596021daa42@samsung.com/ Reviewed-by: Drew Fustini <drew@pdp7.com> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> [drew: remove hunk that included thead,th1520-reset.h] Signed-off-by: Drew Fustini <drew@pdp7.com>
2025-04-25riscv: defconfig: spacemit: enable gpio support for K1 SoCYixun Lan1-0/+1
Enable GPIO support, in order to activate follow-up GPIO LED, and ethernet reset pin. Signed-off-by: Yixun Lan <dlan@gentoo.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-04-25perf/x86: Optimize the is_x86_eventKan Liang1-9/+10
The current is_x86_event has to go through the hybrid_pmus list to find the matched pmu, then check if it's a X86 PMU and a X86 event. It's not necessary. The X86 PMU has a unique type ID on a non-hybrid machine, and a unique capability type. They are good enough to do the check. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20250424134718.311934-5-kan.liang@linux.intel.com
2025-04-25perf/x86/intel: Check the X86 leader for ACR groupKan Liang1-1/+1
The auto counter reload group also requires a group flag in the leader. The leader must be a X86 event. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20250424134718.311934-4-kan.liang@linux.intel.com
2025-04-25Merge branch 'perf/urgent'Peter Zijlstra22-138/+176
Merge urgent fixes for dependencies. Signed-off-by: Peter Zijlstra <peterz@infradead.org>
2025-04-25perf/x86/intel/ds: Fix counter backwards of non-precise events ↵Kan Liang1-2/+19
counters-snapshotting The counter backwards may be observed in the PMI handler when counters-snapshotting some non-precise events in the freq mode. For the non-precise events, it's possible the counters-snapshotting records a positive value for an overflowed PEBS event. Then the HW auto-reload mechanism reset the counter to 0 immediately. Because the pebs_event_reset is cleared in the freq mode, which doesn't set the PERF_X86_EVENT_AUTO_RELOAD. In the PMI handler, 0 will be read rather than the positive value recorded in the counters-snapshotting record. The counters-snapshotting case has to be specially handled. Since the event value has been updated when processing the counters-snapshotting record, only needs to set the new period for the counter via x86_pmu_set_period(). Fixes: e02e9b0374c3 ("perf/x86/intel: Support PEBS counters snapshotting") Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20250424134718.311934-6-kan.liang@linux.intel.com
2025-04-25perf/x86/intel: Check the X86 leader for pebs_counter_event_groupKan Liang1-1/+1
The PEBS counters snapshotting group also requires a group flag in the leader. The leader must be a X86 event. Fixes: e02e9b0374c3 ("perf/x86/intel: Support PEBS counters snapshotting") Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20250424134718.311934-3-kan.liang@linux.intel.com
2025-04-25perf/x86/intel: Only check the group flag for X86 leaderKan Liang2-2/+9
A warning in intel_pmu_lbr_counters_reorder() may be triggered by below perf command. perf record -e "{cpu-clock,cycles/call-graph="lbr"/}" -- sleep 1 It's because the group is mistakenly treated as a branch counter group. The hw.flags of the leader are used to determine whether a group is a branch counters group. However, the hw.flags is only available for a hardware event. The field to store the flags is a union type. For a software event, it's a hrtimer. The corresponding bit may be set if the leader is a software event. For a branch counter group and other groups that have a group flag (e.g., topdown, PEBS counters snapshotting, and ACR), the leader must be a X86 event. Check the X86 event before checking the flag. The patch only fixes the issue for the branch counter group. The following patch will fix the other groups. There may be an alternative way to fix the issue by moving the hw.flags out of the union type. It should work for now. But it's still possible that the flags will be used by other types of events later. As long as that type of event is used as a leader, a similar issue will be triggered. So the alternative way is dropped. Fixes: 33744916196b ("perf/x86/intel: Support branch counters logging") Closes: https://lore.kernel.org/lkml/20250412091423.1839809-1-luogengkun@huaweicloud.com/ Reported-by: Luo Gengkun <luogengkun@huaweicloud.com> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20250424134718.311934-2-kan.liang@linux.intel.com
2025-04-25arm64: dts: imx8mq-evk: add pcie[0,1]-ep nodesFrank Li2-0/+23
Add pcie[0,1]-ep nodes and apply imx-pcie1-ep overlay file. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-04-25arm64: dts: imx8mq: add pcie0-ep nodeFrank Li1-0/+35
Add pcie0-ep node for i.MX8QM. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-04-25arm64: dts: imx8mm-evk: add pcie0-ep node and apply pcie0-ep overlay fileFrank Li2-0/+18
Add pcie0-ep node information and apply pcie0-ep overlay file. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-04-25arm64: dts: imx95: add pcie1 ep overlay file and create pcie-ep dtb filesFrank Li4-0/+42
Create imx95-15x15-evk pcie0-ep and imx95-19x19-evk pcie[0,1]-ep dtb files. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-04-25arm64: dts: imx8: use common imx-pcie0-ep.dtso to enable PCI ep functionFrank Li5-30/+25
Use common imx-pcie0-ep.dtso for imx8mp-evk-pcie-ep and imx8qxp-mek-pcie-ep. No functional change. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-04-25arm64: dts: imx8dxl-evk: Add pcie0-ep node and use unified pcie0 labelFrank Li1-1/+11
Use unified pcie0 label and add pcie0-ep node. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-16 03:39:33 +0300