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2025-05-06x86/bpf: Call branch history clearing sequence on exitDaniel Sneddon1-0/+31
Classic BPF programs have been identified as potential vectors for intra-mode Branch Target Injection (BTI) attacks. Classic BPF programs can be run by unprivileged users. They allow unprivileged code to execute inside the kernel. Attackers can use unprivileged cBPF to craft branch history in kernel mode that can influence the target of indirect branches. Introduce a branch history buffer (BHB) clearing sequence during the JIT compilation of classic BPF programs. The clearing sequence is the same as is used in previous mitigations to protect syscalls. Since eBPF programs already have their own mitigations in place, only insert the call on classic programs that aren't run by privileged users. Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com> Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Acked-by: Daniel Borkmann <daniel@iogearbox.net> Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com>
2025-05-06ARM: shmobile: defconfig: Enable more support for RZN1D-DB/EBGeert Uytterhoeven1-1/+6
Enable more support for the Renesas RZN1D-DB and RZN1D-EB development and expansion boards: - Polled GPIO buttons (also used on the Marzen development board), - Synopsys DesignWare I2C adapters, - National Semiconductor LM75 sensors and compatibles (which requires not disabling Hardware Monitoring support), - Arasan SDHCI controllers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/a40aa69832ef292497b9170e2ad607bd9dfd7e21.1745842538.git.geert+renesas@glider.be
2025-05-06arm64: dts: ti: k3-j721s2: Add GPU nodeMatt Coster1-0/+14
The J721S2 binding is based on the TI downstream binding in commit 54b0f2a00d92 ("arm64: dts: ti: k3-j721s2-main: add gpu node") from [1] but with updated compatible strings. The clock[2] and power[3] indices were verified from HTML docs, while the interrupt index comes from the TRM[4] (appendix "J721S2_Appendix_20241106_Public.xlsx", "Interrupts (inputs)", "GPU_BXS464_WRAP0_GPU_SS_0_OS_IRQ_OUT_0"). [1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel [2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html [3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html [4]: https://www.ti.com/lit/zip/spruj28 (revision E) Reviewed-by: Randolph Sapp <rs@ti.com> Signed-off-by: Matt Coster <matt.coster@imgtec.com> Link: https://lore.kernel.org/r/20250428-bxs-4-64-dts-v4-2-eddafb4ae19f@imgtec.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62: New GPU binding detailsMatt Coster1-1/+3
Use the new compatible string and power domain name as introduced in commit 2c01d9099859 ("dt-bindings: gpu: img: Future-proofing enhancements"). Reviewed-by: Randolph Sapp <rs@ti.com> Signed-off-by: Matt Coster <matt.coster@imgtec.com> Link: https://lore.kernel.org/r/20250428-bxs-4-64-dts-v4-1-eddafb4ae19f@imgtec.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62-main: Add PRUSS-M nodeKishon Vijay Abraham I1-0/+90
Add the DT node for the PRUSS-M processor subsystem that is present on the K3 AM62x SoCs. The K3 AM62x family of SoC has one PRUSS-M instance and it has two Programmable Real-Time Units (PRU0 and PRU1). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [ Judith: Fix pruss_iclk id for pruss_coreclk_mux ] Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Beleswar Padhi <b-padhi@ti.com> Acked-by: Hari Nagalla <hnagalla@ti.com> Link: https://lore.kernel.org/r/20250430144343.972234-1-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am64: Reserve timers used by MCU FWHari Nagalla2-0/+40
AM64x device has 4 R5F cores in the main domain. TI MCU firmware uses main domain timers as tick timers in these firmwares. Hence keep them as reserved in the Linux device tree. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-12-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62a7-sk: Reserve main_rti4 for C7x DSPHari Nagalla1-0/+5
The main rti4 watchdog timer is used by the C7x DSP, so reserve the timer in the linux device tree. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-11-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62a7-sk: Reserve main_timer2 for C7x DSPHari Nagalla1-0/+5
C7x DSP uses main_timer2, so mark it as reserved in linux DT. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-10-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62x-sk-common: Enable IPC with remote processorsHari Nagalla1-5/+29
For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-9-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62p5-sk: Enable IPC with remote processorsDevarsh Thakkar1-6/+44
For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-8-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62a7-sk: Enable IPC with remote processorsDevarsh Thakkar1-6/+90
For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Beleswar Padhi <b-padhi@ti.com> Reviewed-by: Jai Luthra <jai.luthra@ideasonboard.com> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-7-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62a-main: Add C7xv device nodeJai Luthra1-0/+12
AM62A SoCs have a C7xv DSP subsystem with Analytics engine capability. This subsystem is intended for deep learning purposes. Define the device node for C7xv DSP. Signed-off-by: Jai Luthra <j-luthra@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Daniel Schultz <d.schultz@phytec.de> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-6-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62a-wakeup: Add R5F device nodeDevarsh Thakkar1-0/+25
AM62A SoCs have a single R5F core in wakeup domain. This core is also used as a device manager for the SoC. Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Daniel Schultz <d.schultz@phytec.de> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-5-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62a-mcu: Add R5F remote proc nodeHari Nagalla1-0/+25
AM62A SoCs have a single R5F core in the MCU voltage domain. Add the R5FSS node with the child node for core0 in MCU voltage domain .dtsi file. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Daniel Schultz <d.schultz@phytec.de> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-4-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62-wakeup: Add wakeup R5F nodeHari Nagalla1-0/+25
AM62 SoC devices have a single core R5F processor in wakeup domain. The R5F processor in wakeup domain is used as a device manager for the SoC. Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Daniel Schultz <d.schultz@phytec.de> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-3-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62: Add ATCM and BTCM cbass rangesJudith Mendez1-2/+6
Add cbass ranges for ATCM and BTCM on am62x device, without these, remoteproc driver fails to probe and attach to the DM r5 core and IPC communication is broken. Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-2-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am625-beagleplay: Add required voltage supplies for ↵Rishikesh Donadkar1-0/+31
TEVI-OV5640 The device tree overlay for TEVI-OV5640 requires following voltage supplies: AVDD-supply: Analog voltage supply, 2.8 volts DOVDD-supply: Digital I/O voltage supply, 1.8 volts DVDD-supply: Digital core voltage supply, 3.3 volts Add them in the overlay. Signed-off-by: Rishikesh Donadkar <r-donadkar@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Link: https://lore.kernel.org/r/20250506045225.1246873-3-r-donadkar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am625-beagleplay: Add required voltage supplies for OV5640Rishikesh Donadkar1-0/+31
The device tree overlay for OV5640 requires following voltage supplies: AVDD-supply: Analog voltage supply, 2.8 volts DOVDD-supply: Digital I/O voltage supply, 1.8 volts DVDD-supply: Digital core voltage supply, 1.5 volts Add them in the overlay. Signed-off-by: Rishikesh Donadkar <r-donadkar@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Link: https://lore.kernel.org/r/20250506045225.1246873-2-r-donadkar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62x: Add required voltage supplies for TEVI-OV5640Rishikesh Donadkar1-0/+32
The device tree overlay for TEVI-OV5640 requires following voltage supplies as mentioned in the power section [1] AVDD-supply: Analog voltage supply, 2.8 volts DOVDD-supply: Digital I/O voltage supply, 1.8 volts DVDD-supply: Digital core voltage supply, 3.3 volts Add them in the DT overlay. Link: https://www.technexion.com/wp-content/uploads/2023/09/product-brief_tevi-ov5640.pdf Signed-off-by: Rishikesh Donadkar <r-donadkar@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Link: https://lore.kernel.org/r/20250502162539.322091-5-r-donadkar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62x: Add required voltage supplies for OV5640Rishikesh Donadkar1-0/+32
The device tree overlay for OV5640 requires following voltage supplies as mentioned in the table 8-3 of the data-sheet [1]. AVDD-supply: Analog voltage supply, 2.8 volts DOVDD-supply: Digital I/O voltage supply, 1.8 volts DVDD-supply: Digital core voltage supply, 1.5 volts Add them in the overlay. Link: https://cdn.sparkfun.com/datasheets/Sensors/LightImaging/OV5640_datasheet.pdf Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Rishikesh Donadkar <r-donadkar@ti.com> Link: https://lore.kernel.org/r/20250502162539.322091-4-r-donadkar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62x: Add required voltage supplies for IMX219Rishikesh Donadkar1-0/+31
The device tree overlay for the IMX219 sensor requires three voltage supplies to be defined: VANA (analog), VDIG (digital core), and VDDL (digital I/O) [1]. Add the corresponding voltage supply definitions in the overlay so that the same topography as dt-bindings is present in the DT overlay. Link: https://datasheets.raspberrypi.com/camera/camera-module-2-schematics.pdf [1] Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Rishikesh Donadkar <r-donadkar@ti.com> Link: https://lore.kernel.org/r/20250502162539.322091-3-r-donadkar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62p5-sk: Add regulator nodes for AM62PRishikesh Donadkar1-0/+22
Add regulator node for AM62P-SK VCC_3V3_MAIN is the output of LM5141-Q1, and it serves as an input to TPS22965DSGT which produces VCC_3V3_SYS [1] VCC_3V3_SYS servers as vin-supply for peripherals like CSI [1]. Link: https://www.ti.com/lit/zip/sprr487 [1] Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Rishikesh Donadkar <r-donadkar@ti.com> Link: https://lore.kernel.org/r/20250502162539.322091-2-r-donadkar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: cpufeature: Move arm64_use_ng_mappings to the .data section to ↵Yeoreum Yun1-1/+8
prevent wrong idmap generation The PTE_MAYBE_NG macro sets the nG page table bit according to the value of "arm64_use_ng_mappings". This variable is currently placed in the .bss section. create_init_idmap() is called before the .bss section initialisation which is done in early_map_kernel(). Therefore, data/test_prot in create_init_idmap() could be set incorrectly through the PAGE_KERNEL -> PROT_DEFAULT -> PTE_MAYBE_NG macros. # llvm-objdump-21 --syms vmlinux-gcc | grep arm64_use_ng_mappings ffff800082f242a8 g O .bss 0000000000000001 arm64_use_ng_mappings The create_init_idmap() function disassembly compiled with llvm-21: // create_init_idmap() ffff80008255c058: d10103ff sub sp, sp, #0x40 ffff80008255c05c: a9017bfd stp x29, x30, [sp, #0x10] ffff80008255c060: a90257f6 stp x22, x21, [sp, #0x20] ffff80008255c064: a9034ff4 stp x20, x19, [sp, #0x30] ffff80008255c068: 910043fd add x29, sp, #0x10 ffff80008255c06c: 90003fc8 adrp x8, 0xffff800082d54000 ffff80008255c070: d280e06a mov x10, #0x703 // =1795 ffff80008255c074: 91400409 add x9, x0, #0x1, lsl #12 // =0x1000 ffff80008255c078: 394a4108 ldrb w8, [x8, #0x290] ------------- (1) ffff80008255c07c: f2e00d0a movk x10, #0x68, lsl #48 ffff80008255c080: f90007e9 str x9, [sp, #0x8] ffff80008255c084: aa0103f3 mov x19, x1 ffff80008255c088: aa0003f4 mov x20, x0 ffff80008255c08c: 14000000 b 0xffff80008255c08c <__pi_create_init_idmap+0x34> ffff80008255c090: aa082d56 orr x22, x10, x8, lsl #11 -------- (2) Note (1) is loading the arm64_use_ng_mappings value in w8 and (2) is set the text or data prot with the w8 value to set PTE_NG bit. If the .bss section isn't initialized, x8 could include a garbage value and generate an incorrect mapping. Annotate arm64_use_ng_mappings as __read_mostly so that it is placed in the .data section. Fixes: 84b04d3e6bdb ("arm64: kernel: Create initial ID map from C code") Cc: stable@vger.kernel.org # 6.9.x Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com> Link: https://lore.kernel.org/r/20250502180412.3774883-1-yeoreum.yun@arm.com [catalin.marinas@arm.com: use __read_mostly instead of __ro_after_init] [catalin.marinas@arm.com: slight tweaking of the code comment] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2025-05-06x86/insn: Stop decoding i64 instructions in x86-64 mode at opcodeMasami Hiramatsu (Google)4-4/+22
In commit 2e044911be75 ("x86/traps: Decode 0xEA instructions as #UD") FineIBT starts using 0xEA as an invalid instruction like UD2. But insn decoder always returns the length of "0xea" instruction as 7 because it does not check the (i64) superscript. The x86 instruction decoder should also decode 0xEA on x86-64 as a one-byte invalid instruction by decoding the "(i64)" superscript tag. This stops decoding instruction which has (i64) but does not have (o64) superscript in 64-bit mode at opcode and skips other fields. With this change, insn_decoder_test says 0xea is 1 byte length if x86-64 (-y option means 64-bit): $ printf "0:\tea\t\n" | insn_decoder_test -y -v insn_decoder_test: success: Decoded and checked 1 instructions Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/174580490000.388420.5225447607417115496.stgit@devnote2
2025-05-06x86/insn: Fix opcode map (!REX2) superscript tagsMasami Hiramatsu (Google)1-25/+25
Commit: 159039af8c07 ("x86/insn: x86/insn: Add support for REX2 prefix to the instruction decoder opcode map") added (!REX2) superscript with a space, but the correct format requires ',' for concatination with other superscript tags. Add ',' to generate correct insn attribute tables. I confirmed with following command: arch/x86/lib/x86-opcode-map.txt | grep e8 | head -n 1 [0xe8] = INAT_MAKE_IMM(INAT_IMM_VWORD32) | INAT_FORCE64 | INAT_NO_REX2, Fixes: 159039af8c07 ("x86/insn: x86/insn: Add support for REX2 prefix to the instruction decoder opcode map") Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/174580489027.388420.15539375184727726142.stgit@devnote2
2025-05-06Merge tag 'v6.15-rc4' into x86/asm, to pick up fixesIngo Molnar196-825/+1137
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2025-05-06x86/fpu: Drop @perm from guest pseudo FPU containerChao Gao2-12/+2
Remove @perm from the guest pseudo FPU container. The field is initialized during allocation and never used later. Rename fpu_init_guest_permissions() to show that its sole purpose is to lock down guest permissions. Suggested-by: Maxim Levitsky <mlevitsk@redhat.com> Signed-off-by: Chao Gao <chao.gao@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Chang S. Bae <chang.seok.bae@intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Eric Biggers <ebiggers@google.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Kees Cook <kees@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mitchell Levy <levymitchell0@gmail.com> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Samuel Holland <samuel.holland@sifive.com> Cc: Sean Christopherson <seanjc@google.com> Cc: Vitaly Kuznetsov <vkuznets@redhat.com> Link: https://lore.kernel.org/kvm/af972fe5981b9e7101b64de43c7be0a8cc165323.camel@redhat.com/ Link: https://lore.kernel.org/r/20250506093740.2864458-3-chao.gao@intel.com
2025-05-06x86/fpu/xstate: Always preserve non-user xfeatures/flags in __state_permSean Christopherson2-10/+16
When granting userspace or a KVM guest access to an xfeature, preserve the entity's existing supervisor and software-defined permissions as tracked by __state_perm, i.e. use __state_perm to track *all* permissions even though all supported supervisor xfeatures are granted to all FPUs and FPU_GUEST_PERM_LOCKED disallows changing permissions. Effectively clobbering supervisor permissions results in inconsistent behavior, as xstate_get_group_perm() will report supervisor features for process that do NOT request access to dynamic user xfeatures, whereas any and all supervisor features will be absent from the set of permissions for any process that is granted access to one or more dynamic xfeatures (which right now means AMX). The inconsistency isn't problematic because fpu_xstate_prctl() already strips out everything except user xfeatures: case ARCH_GET_XCOMP_PERM: /* * Lockless snapshot as it can also change right after the * dropping the lock. */ permitted = xstate_get_host_group_perm(); permitted &= XFEATURE_MASK_USER_SUPPORTED; return put_user(permitted, uptr); case ARCH_GET_XCOMP_GUEST_PERM: permitted = xstate_get_guest_group_perm(); permitted &= XFEATURE_MASK_USER_SUPPORTED; return put_user(permitted, uptr); and similarly KVM doesn't apply the __state_perm to supervisor states (kvm_get_filtered_xcr0() incorporates xstate_get_guest_group_perm()): case 0xd: { u64 permitted_xcr0 = kvm_get_filtered_xcr0(); u64 permitted_xss = kvm_caps.supported_xss; But if KVM in particular were to ever change, dropping supervisor permissions would result in subtle bugs in KVM's reporting of supported CPUID settings. And the above behavior also means that having supervisor xfeatures in __state_perm is correctly handled by all users. Dropping supervisor permissions also creates another landmine for KVM. If more dynamic user xfeatures are ever added, requesting access to multiple xfeatures in separate ARCH_REQ_XCOMP_GUEST_PERM calls will result in the second invocation of __xstate_request_perm() computing the wrong ksize, as as the mask passed to xstate_calculate_size() would not contain *any* supervisor features. Commit 781c64bfcb73 ("x86/fpu/xstate: Handle supervisor states in XSTATE permissions") fudged around the size issue for userspace FPUs, but for reasons unknown skipped guest FPUs. Lack of a fix for KVM "works" only because KVM doesn't yet support virtualizing features that have supervisor xfeatures, i.e. as of today, KVM guest FPUs will never need the relevant xfeatures. Simply extending the hack-a-fix for guests would temporarily solve the ksize issue, but wouldn't address the inconsistency issue and would leave another lurking pitfall for KVM. KVM support for virtualizing CET will likely add CET_KERNEL as a guest-only xfeature, i.e. CET_KERNEL will not be set in xfeatures_mask_supervisor() and would again be dropped when granting access to dynamic xfeatures. Note, the existing clobbering behavior is rather subtle. The @permitted parameter to __xstate_request_perm() comes from: permitted = xstate_get_group_perm(guest); which is either fpu->guest_perm.__state_perm or fpu->perm.__state_perm, where __state_perm is initialized to: fpu->perm.__state_perm = fpu_kernel_cfg.default_features; and copied to the guest side of things: /* Same defaults for guests */ fpu->guest_perm = fpu->perm; fpu_kernel_cfg.default_features contains everything except the dynamic xfeatures, i.e. everything except XFEATURE_MASK_XTILE_DATA: fpu_kernel_cfg.default_features = fpu_kernel_cfg.max_features; fpu_kernel_cfg.default_features &= ~XFEATURE_MASK_USER_DYNAMIC; When __xstate_request_perm() restricts the local "mask" variable to compute the user state size: mask &= XFEATURE_MASK_USER_SUPPORTED; usize = xstate_calculate_size(mask, false); it subtly overwrites the target __state_perm with "mask" containing only user xfeatures: perm = guest ? &fpu->guest_perm : &fpu->perm; /* Pairs with the READ_ONCE() in xstate_get_group_perm() */ WRITE_ONCE(perm->__state_perm, mask); Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> Signed-off-by: Chao Gao <chao.gao@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com> Reviewed-by: Rick Edgecombe <rick.p.edgecombe@intel.com> Reviewed-by: Chang S. Bae <chang.seok.bae@intel.com> Acked-by: Dave Hansen <dave.hansen@intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: David Woodhouse <dwmw2@infradead.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: John Allen <john.allen@amd.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mitchell Levy <levymitchell0@gmail.com> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Samuel Holland <samuel.holland@sifive.com> Cc: Sohil Mehta <sohil.mehta@intel.com> Cc: Vignesh Balasubramanian <vigbalas@amd.com> Cc: Vitaly Kuznetsov <vkuznets@redhat.com> Cc: Xin Li <xin3.li@intel.com> Cc: kvm@vger.kernel.org Link: https://lore.kernel.org/all/ZTqgzZl-reO1m01I@google.com Link: https://lore.kernel.org/r/20250506093740.2864458-2-chao.gao@intel.com
2025-05-06x86/mm: Fix false positive warning in switch_mm_irqs_off()Peter Zijlstra5-3/+18
Multiple testers reported the following new warning: WARNING: CPU: 0 PID: 0 at arch/x86/mm/tlb.c:795 Which corresponds to: if (IS_ENABLED(CONFIG_DEBUG_VM) && WARN_ON_ONCE(prev != &init_mm && !cpumask_test_cpu(cpu, mm_cpumask(next)))) cpumask_set_cpu(cpu, mm_cpumask(next)); So the problem is that unuse_temporary_mm() explicitly clears that bit; and it has to, because otherwise the flush_tlb_mm_range() in __text_poke() will try sending IPIs, which are not at all needed. See also: https://lore.kernel.org/all/20241113095550.GBZzR3pg-RhJKPDazS@fat_crate.local/ Notably, the whole {,un}use_temporary_mm() thing requires preemption to be disabled across it with the express purpose of keeping all TLB nonsense CPU local, such that invalidations can also stay local etc. However, as a side-effect, we violate this above WARN(), which sorta makes sense for the normal case, but very much doesn't make sense here. Change unuse_temporary_mm() to mark the mm_struct such that a further exception (beyond init_mm) can be grafted, to keep the warning for all the other cases. Reported-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reported-by: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Andrew Cooper <andrew.cooper3@citrix.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Brian Gerst <brgerst@gmail.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Juergen Gross <jgross@suse.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Rik van Riel <riel@surriel.com> Link: https://lore.kernel.org/r/20250430081154.GH4439@noisy.programming.kicks-ass.net
2025-05-06KVM: arm64: Extend pKVM selftest for np-guestsQuentin Perret5-5/+104
The pKVM selftest intends to test as many memory 'transitions' as possible, so extend it to cover sharing pages with non-protected guests, including in the case of multi-sharing. Signed-off-by: Quentin Perret <qperret@google.com> Link: https://lore.kernel.org/r/20250416160900.3078417-5-qperret@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-05-06KVM: arm64: Selftest for pKVM transitionsQuentin Perret3-0/+119
We have recently found a bug [1] in the pKVM memory ownership transitions by code inspection, but it could have been caught with a test. Introduce a boot-time selftest exercising all the known pKVM memory transitions and importantly checks the rejection of illegal transitions. The new test is hidden behind a new Kconfig option separate from CONFIG_EL2_NVHE_DEBUG on purpose as that has side effects on the transition checks ([1] doesn't reproduce with EL2 debug enabled). [1] https://lore.kernel.org/kvmarm/20241128154406.602875-1-qperret@google.com/ Suggested-by: Will Deacon <will@kernel.org> Signed-off-by: Quentin Perret <qperret@google.com> Link: https://lore.kernel.org/r/20250416160900.3078417-4-qperret@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-05-06KVM: arm64: Don't WARN from __pkvm_host_share_guest()Quentin Perret1-1/+0
We currently WARN() if the host attempts to share a page that is not in an acceptable state with a guest. This isn't strictly necessary and makes testing much harder, so drop the WARN and make sure to propage the error code instead. Signed-off-by: Quentin Perret <qperret@google.com> Link: https://lore.kernel.org/r/20250416160900.3078417-3-qperret@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-05-06KVM: arm64: Add .hyp.data sectionDavid Brazdil7-3/+32
The hypervisor has not needed its own .data section because all globals were either .rodata or .bss. To avoid having to initialize future data-structures at run-time, let's introduce add a .data section to the hypervisor. Signed-off-by: David Brazdil <dbrazdil@google.com> Signed-off-by: Quentin Perret <qperret@google.com> Link: https://lore.kernel.org/r/20250416160900.3078417-2-qperret@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-05-06KVM: arm64: Force HCR_EL2.xMO to 1 at all times in VHE modeMarc Zyngier2-16/+22
We keep setting and clearing these bits depending on the role of the host kernel, mimicking what we do for nVHE. But that's actually pretty pointless, as we always want physical interrupts to make it to the host, at EL2. This has also two problems: - it prevents IRQs from being taken when these bits are cleared if the implementation has chosen to implement these bits as masks when HCR_EL2.{TGE,xMO}=={0,0} - it triggers a bad erratum on the AmpereOne HW, which catches fire on clearing these bits while an interrupt is being taken (AC03_CPU_36). Let's kill these two birds with a single stone, and permanently set the xMO bits when running VHE. This involves a bit of surgery on code paths that rely on flipping these bits on and off for other purposes. Note that the earliest setting of hcr_el2 (in the init_hcr_el2 macro) is left untouched as is runs extremely early, with interrupts disabled, and soon enough overwritten with the final value containing the xMO bits. Reported-by: D Scott Phillips <scott@os.amperecomputing.com> Link: https://lore.kernel.org/r/20250429114326.3618875-1-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-05-06KVM: arm64: Replace ternary flags with str_on_off() helperSeongsu Park1-3/+3
Replace repetitive ternary expressions with the str_on_off() helper function. This change improves code readability and ensures consistency in tracepoint string formatting Signed-off-by: Seongsu Park <sgsu.park@samsung.com> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/1891546521.01744691102904.JavaMail.epsvc@epcpadp1new Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-05-06arm64: dts: mt6359: Add missing 'compatible' property to regulators nodeJulien Massot1-0/+2
The 'compatible' property is required by the 'mfd/mediatek,mt6397.yaml' binding. Add it to fix the following dtb-check error: mediatek/mt8395-radxa-nio-12l.dtb: pmic: regulators: 'compatible' is a required property Fixes: 3b7d143be4b7 ("arm64: dts: mt6359: add PMIC MT6359 related nodes") Signed-off-by: Julien Massot <julien.massot@collabora.com> Link: https://lore.kernel.org/r/20250505-mt8395-dtb-errors-v1-3-9c4714dcdcdb@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-06arm/arm64: dts: mediatek: Add missing "#sound-dai-cells" to linux,bt-scoRob Herring (Arm)2-0/+2
Add missing "#sound-dai-cells" which is required by the linux,bt-sco binding. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250409205001.1522009-1-robh@kernel.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-06arm64: dts: mediatek: mt8390-genio-common: Set ssusb2 default dual role mode ↵Louis-Alexis Eyraud1-1/+11
to host On the Mediatek Genio 510-EVK and 700-EVK boards, ssusb2 controller is one but has two ports: one is routed to the M.2 slot, the other is on the RPi header who does support full OTG. Since Mediatek Genio 700-EVK USB support was added, dual role mode property is set to otg for ssusb2. This config prevents the M.2 Wifi/Bluetooth module, present on those boards and exposing Bluetooth as an USB device to be properly detected at startup as the default role is device. To keep the OTG functionality and make the M.2 module be detected at the same time, add role-switch-default-mode property set to host and also fix the polarity of GPIO associated to the USB connector, so the ssusb2 controller role is properly set to host when the other port is unused. Fixes: 1afaeca17238 ("arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller, MUX") Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Link: https://lore.kernel.org/r/20250502-mtk-genio-510-700-fix-bt-detection-v2-1-870aa2145480@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-06arm64: dts: mediatek: mt8395-genio-1200-evk: Disable unused backlightNícolas F. R. A. Prado1-0/+1
The builtin panel on the Genio 1200 EVK board uses the backlight_lcm0 node for its backlight. Though the backlight_lcd1 is currently left enabled, it is unused, and its pwm input, disp_pwm1, is disabled, so it fails probe. Disable this unused node. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20250502-genio-1200-disable-backlight-lcd1-v1-1-c021d2c9e48e@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-06arm64: dts: mediatek: mt6357: Drop regulator-fixed compatiblesNícolas F. R. A. Prado1-10/+0
Some of the regulators in the MT6357 PMIC dtsi have compatible set to regulator-fixed, even though they don't serve any purpose: all those regulators are handled as a whole by the mt6357-regulator driver. In fact this is the only dtsi in this family of chips where this is the case: mt6359 and mt6358 don't have any such compatibles. A side-effect caused by this is that the DT kselftest, which is supposed to identify nodes with compatibles that can be probed, but haven't, shows these nodes as failures. Remove the useless compatibles to move the dtsi in line with the others in its family and fix the DT kselftest failures. Fixes: 55749bb478f8 ("arm64: dts: mediatek: add mt6357 device-tree") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20250502-mt6357-regulator-fixed-compatibles-removal-v1-1-a582c16743fe@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-06arm64: dts: rockchip: Enable regulators for Radxa E20CChukun Pan1-0/+73
Enable pwm and fixed regulators for Radxa E20C. The pwm regulator is used to power the CPU and GPU. Note that the LPDDR4 voltage is 1.1V. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250401120020.976343-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-06arm64: dts: rockchip: Add pwm nodes for RK3528Chukun Pan1-0/+80
Add pwm nodes for RK3528. The PWM core on RK3528 is the same as RK3328, but the driver does not support interrupts yet. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250401120020.976343-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-06x86/cpu: Sanitize CPUID(0x80000000) outputAhmed S. Darwish1-8/+9
CPUID(0x80000000).EAX returns the max extended CPUID leaf available. On x86-32 machines without an extended CPUID range, a CPUID(0x80000000) query will just repeat the output of the last valid standard CPUID leaf on the CPU; i.e., a garbage values. Current tip:x86/cpu code protects against this by doing: eax = cpuid_eax(0x80000000); c->extended_cpuid_level = eax; if ((eax & 0xffff0000) == 0x80000000) { // CPU has an extended CPUID range. Check for 0x80000001 if (eax >= 0x80000001) { cpuid(0x80000001, ...); } } This is correct so far. Afterwards though, the same possibly broken EAX value is used to check the availability of other extended CPUID leaves: if (c->extended_cpuid_level >= 0x80000007) ... if (c->extended_cpuid_level >= 0x80000008) ... if (c->extended_cpuid_level >= 0x8000000a) ... if (c->extended_cpuid_level >= 0x8000001f) ... which is invalid. Fix this by immediately setting the CPU's max extended CPUID leaf to zero if CPUID(0x80000000).EAX doesn't indicate a valid CPUID extended range. While at it, add a comment, similar to kernel/head_32.S, clarifying the CPUID(0x80000000) sanity check. References: 8a50e5135af0 ("x86-32: Use symbolic constants, safer CPUID when enabling EFER.NX") Fixes: 3da99c977637 ("x86: make (early)_identify_cpu more the same between 32bit and 64 bit") Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Andrew Cooper <andrew.cooper3@citrix.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: John Ogness <john.ogness@linutronix.de> Cc: x86-cpuid@lists.linux.dev Link: https://lore.kernel.org/r/20250506050437.10264-3-darwi@linutronix.de
2025-05-06Merge tag 'v6.15-rc5' into x86/cpu, to resolve conflictsIngo Molnar204-847/+1242
Conflicts: tools/arch/x86/include/asm/cpufeatures.h Signed-off-by: Ingo Molnar <mingo@kernel.org>
2025-05-06powerpc/boot: Fix build with gcc 15Michal Suchanek1-0/+1
Similar to x86 the ppc boot code does not build with GCC 15. Copy the fix from commit ee2ab467bddf ("x86/boot: Use '-std=gnu11' to fix build with GCC 15") Signed-off-by: Michal Suchanek <msuchanek@suse.de> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Tested-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20250331105722.19709-1-msuchanek@suse.de
2025-05-06arm64: dts: rockchip: Add onboard EEPROM for Radxa E20CYao Zi1-0/+14
Radxa E20C ships an onboard I2C EEPROM for storing production information. Enable it in devicetree. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250417120118.17610-6-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-06arm64: dts: rockchip: Add I2C controllers for RK3528Yao Zi1-0/+110
Describe I2C controllers shipped by RK3528 in devicetree. For I2C-2, I2C-4 and I2C-7 which come with only a set of possible pins, a default pin configuration is included. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250417120118.17610-5-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-05block: remove bounce buffering supportChristoph Hellwig1-1/+0
The block layer bounce buffering support is unused now, remove it. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Hannes Reinecke <hare@suse.de> Reviewed-by: John Garry <john.g.garry@oracle.com> Reviewed-by: Johannes Thumshirn <johannes.thumshirn@wdc.com> Link: https://lore.kernel.org/r/20250505081138.3435992-7-hch@lst.de Signed-off-by: Jens Axboe <axboe@kernel.dk>
2025-05-05arm64: tegra: tegra210-p2894: Align GPIO hog node name with preferred styleKrzysztof Kozlowski1-1/+1
GPIO hogs device node names can use 'hog' prefix or suffix, but the suffix is preferred. The pattern in DT schema might narrow in the future, so adjust the DTS now. Link: https://lore.kernel.org/r/20250115204603.136997-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-05KVM: arm64: Prevent userspace from disabling AArch64 support at any ↵Marc Zyngier1-0/+6
virtualisable EL A sorry excuse for a selftest is trying to disable AArch64 support. And yes, this goes as well as you can imagine. Let's forbid this sort of things. Normal userspace shouldn't get caught doing that. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com> Link: https://lore.kernel.org/r/20250429114117.3618800-2-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>