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Following the change to emphasize L2 cache compatibility in Dubhe
cache controller, update the compatible string to reflect the changes.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
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Dubhe QSPI uses 64KB erase sector by default and causes MTD driver to
warn about "partition doesn't start on an erase/write block boundary --
force read-only", changing r/w partition to read only to avoid
unintended access to adjacent partition.
Update the erase sector size to 4KB to ensure the partition size is
multiple of flash block-size to meet the flash block boundary
requirement, and allowing r/w access to the QSPI partition.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
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Needed to properly forward TFTP to KVM guest behind NAT, by marking
packets to use TFTP-specific NAT helper module.
Usage example (setup in host before starting guest):
modprobe nf_nat_tftp
iptables -t raw -I PREROUTING -j CT -p udp -m udp --dport 69 --helper tftp
Signed-off-by: Tan En De <ende.tan@starfivetech.com>
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Add ZICBOP isa-extension support for Dubhe-70.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
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The cost of changing a cacheline from shared to exclusive state can be
significant, especially when this is triggered by an exclusive store,
since it may result in having to retry the transaction.
This patch makes use of prefetch.w to prefetch cachelines for write
prior to lr/sc loops when using the xchg_small atomic routine.
This patch is inspired by commit: 0ea366f5e1b6 ("arm64: atomics:
prefetch the destination word for write prior to stxr").
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
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Enable Linux prefetchw primitive with Zicbop cpufeature, which preloads
cache line into L1 cache for the next write operation.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
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Cache-block prefetch instructions are HINTs to the hardware to
indicate that software intends to perform a particular type of
memory access in the near future. This patch adds prefetch.i,
prefetch.r and prefetch.w instruction definitions by
RISCV_ISA_EXT_ZICBOP cpufeature.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
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xchg for variables of size 1-byte and 2-bytes is not yet available for
riscv, even though its present in other architectures such as arm64 and
x86. This could lead to not being able to implement some locking mechanisms
or requiring some rework to make it work properly.
Implement 1-byte and 2-bytes xchg in order to achieve parity with other
architectures.
Signed-off-by: Leonardo Bras <leobras@redhat.com>
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cmpxchg for variables of size 1-byte and 2-bytes is not yet available for
riscv, even though its present in other architectures such as arm64 and
x86. This could lead to not being able to implement some locking mechanisms
or requiring some rework to make it work properly.
Implement 1-byte and 2-bytes cmpxchg in order to achieve parity with other
architectures.
Signed-off-by: Leonardo Bras <leobras@redhat.com>
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Some functions use mostly the same asm for 32-bit and 64-bit versions.
Make a macro that is generic enough and avoid code duplication.
(This did not cause any change in generated asm)
Signed-off-by: Leonardo Bras <leobras@redhat.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
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In this header every cmpxchg define (_relaxed, _acquire, _release,
vanilla) contain it's own asm file, both for 4-byte variables an 8-byte
variables, on a total of 8 versions of mostly the same asm.
This is usually bad, as it means any change may be done in up to 8
different places.
Unify those versions by creating a new define with enough parameters to
generate any version of the previous 8.
Then unify the result under a more general define, and simplify
arch_cmpxchg* generation
(This did not cause any change in generated asm)
Signed-off-by: Leonardo Bras <leobras@redhat.com>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
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In this header every xchg define (_relaxed, _acquire, _release, vanilla)
contain it's own asm file, both for 4-byte variables an 8-byte variables,
on a total of 8 versions of mostly the same asm.
This is usually bad, as it means any change may be done in up to 8
different places.
Unify those versions by creating a new define with enough parameters to
generate any version of the previous 8.
Then unify the result under a more general define, and simplify
arch_xchg* generation.
(This did not cause any change in generated asm)
Signed-off-by: Leonardo Bras <leobras@redhat.com>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
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Remove unused clock "gtxc".
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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When svinval is supported the local_flush_tlb_page*
functions would prefer to use the following sequence
to optimize the tlb flushes instead of a simple sfence.vma:
sfence.w.inval
svinval.vma
.
.
svinval.vma
sfence.inval.ir
The maximum number of consecutive svinval.vma instructions
that can be executed in local_flush_tlb_page* functions is
limited to 64. This is required to avoid soft lockups and the
approach is similar to that used in arm64.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
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Add zihintpause isa-extension which is supported in Dubhe-80 and Dubhe-90
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
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Fix DT binding check errors. Change "b" to "zba", "zbb", "zbc" and "zbs".
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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Dubhe-80 and Dubhe-70 use private L2, Dubhe-90 uses shared L2.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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Update StarFive's Dubhe80 and Dubhe90 device tree to use riscv,isa-base
and riscv,extensions property to express RISC-V profiles and extensions
supported by the platforms.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
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Add device tree support for StarFive's Dubhe-70.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
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CPU core that supports H-extension v0.6.1 does not have henvcfg and
senvcfg CSR register support, accessing it will cause kernel to throw
illegal access warning.
This patch introduce errata for platform that does not support accessing
the CSR by bypassing it through the usage of static key.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
Signed-off-by: Tan En De <ende.tan@starfivetech.com>
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[ Upstream commit df68f4d8cb49 ]
We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable Zicond extension for Guest/VM.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
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[ Upstream commit c04913f2b54e ]
Add support for sstateen0 CSR to the ONE_REG interface to allow its
access from user space.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
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[ Upstream commit 81f0f314fec9 ]
Define sstateen0 and add sstateen0 save/restore for guest VCPUs.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
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[ Upstream commit db3c01c7a308 ]
Add senvcfg context save/restore for guest VCPUs and also add it to the
ONE_REG interface to allow its access from user space.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
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[ Upstream commit d21b5d342fc1 ]
Configure hstateen0 register so that the AIA state and envcfg are
accessible to the vcpus. This includes registers such as siselect,
sireg, siph, sieh and all the IMISC registers.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
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[ Upstream commit fe0bab701e3b ]
Add a placeholder for all registers such as henvcfg, hstateen etc
which have 'static' configurations depending on extensions supported by
the guest. The values are derived once and are then subsequently written
to the corresponding CSRs while switching to the vcpu.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
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[ Upstream commit 662a601aa355 ]
The RISC-V integer conditional (Zicond) operation extension defines
standard conditional arithmetic and conditional-select/move operations
which are inspired from the XVentanaCondOps extension. In fact, QEMU
RISC-V also has support for emulating Zicond extension.
Let us detect Zicond extension from ISA string available through
DT or ACPI.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
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[ Upstream commit 9dbaf381008d ]
Extend the ISA string parsing to detect the Smstateen extension. If the
extension is enabled then access to certain 'state' such as AIA CSRs in
VS mode is controlled by *stateen0 registers.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
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[ Upstream commit 43c16d51a19b ]
When Zicboz is present, enable its instruction (cbo.zero) in
usermode by setting its respective senvcfg bit. We don't bother
trying to set this bit per-task, which would also require an
interface for tasks to request enabling and/or disabling. Instead,
permanently set the bit for each hart which has the extension when
bringing it online.
This patch also introduces riscv_cpu_has_extension_[un]likely()
functions to check a specific hart's ISA bitmap for extensions.
Prior to checking the specific hart's bitmap in these functions
we try the bitmap which represents the LCD of extensions, but only
when we know it will use its optimized, alternatives path by gating
its call on CONFIG_RISCV_ALTERNATIVE. When alternatives are used, the
compiler ensures that the invocation of the LCD search becomes a
constant true or false. When it's true, even the new functions will
completely vanish from their callsites. OTOH, when the LCD check is
false, we need to do a search of the hart's ISA bitmap. Had we also
checked the LCD bitmap without the use of alternatives, then we would
have ended up with two bitmap searches instead of one.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230918131518.56803-10-ajones@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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[ Upstream commit 181f2a28d688 ]
commit c818fea83de4 ("riscv: say disabling zicbom if no or bad
riscv,cbom-block-size found") improved the error messages for
zicbom but zicboz was missed since its patches were in flight
at the same time. Get 'em now.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230918131518.56803-9-ajones@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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This reverts commit d181fd3d146844db2d5095ae208b8664160e4eb0.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
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kvm_riscv_vcpu_update_config()"
This reverts commit 081a4205bbea5784e9815e6fd11d7b865cd6b9ff.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
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[ Upstream commit 9c7646d5ffd2b8bf720a0b77897f6c5095dfc53b ]
Expose Zicboz through hwprobe and also provide a key to extract its
respective block size. Opportunistically add a macro and apply it to
current extensions in order to avoid duplicating code.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230918131518.56803-11-ajones@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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PMU hardware is in the CPU core, move the pmu DT node out of the soc node.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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Add cpu-map DT node.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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Change to "starfive,dubhe-80" and "starfive,dubhe-90" compatible strings.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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This patch updates QSPI partition to allow MTD util to update the
content inside the QSPI flash.
The QSPI partition are arranged as follow:
QSPI Flash content | Start Addr | End Addr | Size |
--------------------------------------------------------
Boot Copier(RO) | 0x00000000 | 0x00000fff | 4KB |
Boot Jump Code(RO) | 0x00001000 | 0x00001fff | 4KB |
U-Boot SPL | 0x00002000 | 0x00041fff | 256KB |
U-Boot FIT Image | 0x00042000 | 0x00141fff | 1MB |
Linux + Rootfs | 0x00142000 | 0x07ffffff | 126MB |
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
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So that we can create virtual network consisting of bridge and
TAP interface attached to the bridge as a port.
Signed-off-by: Tan En De <ende.tan@starfivetech.com>
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Add Dubhe 80 DT support.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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Move Dubhe FPGA common DT to *common.dtsi file, in preparation for Dubhe 80.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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- Add cpu0 and cpu1 label
- Update D cache and I cache settings
- Update "riscv,isa", remove unused 'n'.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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Restructure the Dubhe device tree in preparation for Dubhe 80 support.
Rename existing Dubhe to Dubhe 90.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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Add sscofpmf extension support and interrupt register.
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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Commit 338a93e3aea9 ("arch: riscv: kvm: Temporarily comment out
henvcfg-related code") has commented out calling to
kvm_riscv_vcpu_update_config() function. So, comment out
kvm_riscv_vcpu_update_config() function to resolve unused function
warning.
arch/riscv/kvm/vcpu.c:807:13: warning: 'kvm_riscv_vcpu_update_config' defined
but not used [-Wunused-function]
807 | static void kvm_riscv_vcpu_update_config(const unsigned long *isa)
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Fixes: 338a93e3aea9 ("arch: riscv: kvm: Temporarily comment out henvcfg-related code")
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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Add SBI console configs support
Signed-off-by: Tan En De <ende.tan@starfivetech.com>
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Change PMU event mapping based on updated Dubhe Q2 2023 release
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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Use marvell,reg-init node in mdio PHY to update the PHY settings
for StarFive Dubhe platform.
The following settings are enabled:
PAUSE+
ADVERTISED SPEED 10MBPS +
COPPER MODE+
AUTONEGOTIATION+
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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Removes server ip address field from bootargs ip.
Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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This patch includes flash partition changes.
Signed-off-by: Yang Lee <yang.lee@starfivetech.com>
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Enable KVM as builtin module.
Signed-off-by: Tan En De <ende.tan@starfivetech.com>
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