| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-04-24 | [DMA] : Add standard system clock tree & reset API | curry.zhang | 1 | -1/+6 | |
| Signed-off-by: curry.zhang <curry.zhang@starfivetech.com> | |||||
| 2022-04-24 | dt-bingings:uart:jh7110: add clks and reset signals to uarts | yanhong.wang | 2 | -11/+16 | |
| Uart uses the clock and reset framework API. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com> | |||||
| 2022-04-22 | dt-bingings:clk: remove venc_rootclk fixed clk define. | samin | 1 | -6/+0 | |
| The clktree is ready. The Venc uses the clock signal defined by the clock tree, fixed-clk is not required. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-04-22 | dt-bingings:venc:jh7110: Add CLK signals to Venc. | samin | 1 | -4/+22 | |
| Venc uses the Clock framework API. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-04-22 | Merge branch 'CR_835_JPU_samin.guo' into 'jh7110_fpga_dev_5.15' | andy.hu | 2 | -11/+5 | |
| Cr 835 jpu samin.guo See merge request sdk/sft-riscvpi-linux-5.10!14 | |||||
| 2022-04-22 | riscv: dts: jh7110: Add syscon support | mason.huo | 1 | -0/+15 | |
| Add 'stg', 'sys', 'aon' system control register support, access these registers through syscon framework. Signed-off-by: mason.huo <mason.huo@starfivetech.com> | |||||
| 2022-04-21 | dt-bingings:clk: remove jpu_rootclk fixed clk define. | samin | 1 | -6/+0 | |
| The clktree is ready. The JPU uses the clock signal defined by the clock tree, fixed-clk is not required. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-04-21 | dt-bingings:jpu:jh7110: Add CLK signals to JPU. | samin | 1 | -5/+5 | |
| Jpu uses the Clock framework API. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-04-21 | Merge branch 'CR_866_SDIO_clivia.cai' into 'jh7110_fpga_dev_5.15' | andy.hu | 1 | -1/+4 | |
| dt-bingings:sd:update jh7110 sd dt-bingings See merge request sdk/sft-riscvpi-linux-5.10!17 | |||||
| 2022-04-21 | arch:riscv:modify Kconfig.socs | xingyu.wu | 1 | -23/+0 | |
| Kconfig.socs: remove the definitions like 'STARFIVE_BOARD_FPGA'. drivers:watchdog: change the definition. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> | |||||
| 2022-04-20 | dt-bingings:emmc:update jh7110 emmc dt-bingings | Clivia.Cai | 1 | -1/+5 | |
| Add clock and reset for sdio0 nodes in device tree Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com> | |||||
| 2022-04-20 | dt-bingings:sd:update jh7110 sd dt-bingings | Clivia.Cai | 1 | -1/+4 | |
| Add clock and reset for sdio1 nodes in device tree Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com> | |||||
| 2022-04-19 | driver:watchdog:Add config definition to different uses of board level | xingyu.wu | 1 | -15/+15 | |
| 1. The watchdog driver can get different rate from clock by different board. 2. arch:riscv:Kconfig: Adjust the format. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> | |||||
| 2022-04-19 | driver:watchdog: Add clock & reset | xingyu.wu | 1 | -1/+7 | |
| Add clock and reset in watchdog's driver and device tree. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> | |||||
| 2022-04-19 | clk:starfive: Adjust the format | xingyu.wu | 1 | -2/+2 | |
| Adjust and modify the clock driver's format Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> | |||||
| 2022-04-19 | dt-bingings:can:update jh7110 can dt-bingings. | Clivia.Cai | 1 | -7/+35 | |
| Update jh7110 can/canfd dt-bindings configuration Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com> | |||||
| 2022-04-19 | riscv:defconfig: enable CAN,IPMS_CAN | Clivia.Cai | 1 | -1/+2 | |
| Enable can/canfd config in defconfig. Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com> | |||||
| 2022-04-19 | Merge branch 'CR_870_Reset_samin.guo' into 'jh7110_fpga_dev_5.15' | andy.hu | 1 | -2/+2 | |
| Cr 870 reset samin.guo See merge request sdk/sft-riscvpi-linux-5.10!11 | |||||
| 2022-04-19 | reset:starfive:jh7110: Fix wrong macro definition. | samin | 1 | -2/+2 | |
| Fix wrong macro definition. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-04-18 | dt-bingings:clk: remove dec_rootclk fixed clk define. | samin | 1 | -6/+0 | |
| The clktree is ready. The VDEC uses the clock signal defined by the clock tree, fixed-clk is not required. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-04-18 | dt-bingings:vdec:jh7110: Add CLK signals to Vdec | samin | 1 | -4/+9 | |
| Vdec uses the Clock framework API. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-04-14 | riscv: dts: starfive: Improve the structure of device tree | Hal Feng | 9 | -661/+832 | |
| Divide the old device tree into several files according to different layers. Make the device tree clearer and more readable. Signed-off-by: Hal Feng <hal.feng@starfivetech.com> | |||||
| 2022-04-14 | modify vin pinctrl dts | jianlong.huang | 1 | -1/+1 | |
| Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com> | |||||
| 2022-04-13 | add dvp pinctrl dts | jianlong.huang | 1 | -0/+107 | |
| Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com> | |||||
| 2022-04-13 | arch:riscv:Kconfig: Add choice with SOC board type | xingyu.wu | 1 | -0/+23 | |
| Add config about user can choose the board type about FPGA, EVB or Visionfive Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> | |||||
| 2022-04-13 | clk:starfive: Add vout clock tree driver | xingyu.wu | 1 | -0/+1 | |
| Clock references refer to include/dt-bindings/clock/starfive-jh7110-vout.h Change the value about 'status' of clkvout node in dts file when want to use vout clock. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> | |||||
| 2022-04-13 | clk:starfive: Add JH7110 clock tree driver for kernel 5.15 | xingyu.wu | 2 | -13/+175 | |
| Add clock driver about sys, stg and aon clock for JH7110. Clock references refer to include/dt-bindings/clock/starfive-jh7110-clkgen.h Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> | |||||
| 2022-04-12 | enable sdio pinctrcl | jianlong.huang | 1 | -0/+12 | |
| Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com> | |||||
| 2022-04-07 | enable pinctrl and modify gpio irq init | jianlonghuang | 2 | -4/+7 | |
| Signed-off-by: jianlonghuang <jianlong.huang@starfivetech.com> | |||||
| 2022-04-07 | [pinctrl]Synchronize vic7100&jh7110 pinctrl subsystem | “jenny.zhang” | 1 | -0/+8 | |
| 2022-04-07 | [pinctrl] disable jh7110 pinctrl | “jenny.zhang” | 1 | -1/+1 | |
| 2022-04-07 | [pinctrl] 1.Update jh7110 pinctrl dts; 2.Adjust pinctrl coding style; | “jenny.zhang” | 1 | -0/+14 | |
| 2022-04-07 | [pinctrl] add jh7110 pinctrl dts and driver | “jenny.zhang” | 1 | -0/+388 | |
| 2022-01-14 | riscv:uboot:starfive:dc8200 | keith.zhao | 1 | -0/+109 | |
| update drdc8200iver kenerl version from 5.10 to 5.13 Signed-off-by:keith.zhao<keith.zhao@statfivetech.com> | |||||
| 2022-01-14 | dt-bingings:pmu:add jh7110 pmu dt-bingings. | samin | 1 | -0/+8 | |
| Add jh7110 pmu support. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2022-01-13 | 1.add mailbox driver; 2.add mailbox test driver. | shanlong.li | 2 | -1/+19 | |
| 2022-01-12 | v4l2: add mipi pipeline suppport and ov13850 sensor | changhuang.liang | 1 | -26/+58 | |
| 2022-01-06 | [v4l2][update kernel5.15] | david.li | 1 | -1/+1 | |
| 2022-01-05 | dt-bingings:reset:jh7110: Add isp/vout reg reset node. | samin | 1 | -2/+4 | |
| Add isp/vout reg reset node for jh7110. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2021-12-23 | open pcie | david.li | 1 | -1/+0 | |
| 2021-12-22 | dt-bingings:reset: Add reset node for vdec&&jpeg. | samin | 1 | -0/+16 | |
| Add reset bindings for the vdec&jpeg. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2021-12-22 | dt-bingings:reset: Add Starfive JH7110 reset bindings | samin | 1 | -2/+7 | |
| Add bindings for the reset controller on the JH7110 RISC-V SoC by StarFive Ltd. Signed-off-by: samin <samin.guo@starfivetech.com> | |||||
| 2021-12-20 | [pwm] Add jh7110 pwm driver code | “jenny.zhang” | 1 | -0/+9 | |
| 2021-12-16 | [can] Add jh7110 can driver code | “jenny.zhang” | 1 | -0/+19 | |
| 2021-12-16 | [trng] Add jh7110 trng driver code | “jenny.zhang” | 1 | -0/+11 | |
| 2021-12-16 | [alsa] Add jh7110 audio module driver code | “jenny.zhang” | 1 | -0/+135 | |
| 2021-12-14 | [add v4l2 driver && close pcie] | david.li | 3 | -1/+94 | |
| 2021-12-13 | modified dts file for jh7110 i2c | Huan.Feng | 1 | -1/+17 | |
| 2021-12-10 | remove IMG-rogue and null-disp and drm_legacy | vincent.zhang | 1 | -2/+1 | |
| Signed-off-by: vincent.zhang <vincent.zhang@starfivetech.com> | |||||
| 2021-12-10 | add IMG-rogue, DRM, GEM & KMS, enable DRM legacy for default config | vincent.zhang | 1 | -3/+5 | |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |