| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-05-05 | Merge branch 'CR_868_USB-HOST_yanhong.wang' into 'jh7110_fpga_dev_5.15' | andy.hu | 2 | -13/+30 | |
| Cr 868 usb host yanhong.wang See merge request sdk/sft-riscvpi-linux-5.10!44 | |||||
| 2022-05-05 | Audio pdm: add clock/reset/pinctrl initialization | Walker Chen | 2 | -3/+39 | |
| Signed-off-by: Walker Chen <walker.chen@starfivetech.com> | |||||
| 2022-05-05 | dt-bingings:usb: Add usb device node | yanhong.wang | 2 | -13/+30 | |
| Add usb device node configuration for JH7110 SoC platform. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com> | |||||
| 2022-05-05 | [Audio: SPDIF] Add standard system clock tree API | curry.zhang | 1 | -2/+6 | |
| Signed-off-by: curry.zhang <curry.zhang@starfivetech.com> | |||||
| 2022-05-05 | spi: Add clock, reset and pinctrl | xingyu.wu | 2 | -9/+17 | |
| driver:spi: Add reset handle. dts:starfive:dtsi: Add clock and reset node. dts:starfive:pinctrl: Modify spi gpio and Add pinctrl. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> | |||||
| 2022-05-04 | [Audio] I2S and WM8960 | curry.zhang | 3 | -10/+81 | |
| 1) Add standard system clock tree API 2) Modify wm8960 and I2S drivers Signed-off-by: curry.zhang <curry.zhang@starfivetech.com> | |||||
| 2022-04-28 | Merge branch 'CR_907_GPU_shanlong.li' into 'jh7110_fpga_dev_5.15' | andy.hu | 1 | -2/+13 | |
| Cr 907 gpu shanlong.li See merge request sdk/sft-riscvpi-linux-5.10!37 | |||||
| 2022-04-28 | Merge branch 'CR_873_HIFI4_henry.qin' into 'jh7110_fpga_dev_5.15' | andy.hu | 2 | -0/+29 | |
| Cr 873 hifi4 henry.qin See merge request sdk/sft-riscvpi-linux-5.10!31 | |||||
| 2022-04-28 | Merge branch 'CR_845_FPGA-V1.0-VIN_update_changhuang.liang' into ↵ | andy.hu | 3 | -10/+132 | |
| 'jh7110_fpga_dev_5.15' Cr 845 fpga v1.0 vin update changhuang.liang See merge request sdk/sft-riscvpi-linux-5.10!35 | |||||
| 2022-04-28 | Merge branch 'CR_737_CLOCK_TREE_Xingyu.Wu' into 'jh7110_fpga_dev_5.15' | andy.hu | 1 | -0/+10 | |
| clk:starfive: Add isp clock tree driver See merge request sdk/sft-riscvpi-linux-5.10!32 | |||||
| 2022-04-28 | HIFI4: Add hifi4 clk and rst, del unused code, resolve code review | henry.qin | 2 | -0/+29 | |
| problems, change file access mode. Signed-off-by: henry.qin <henry.qin@starfivetech.com> | |||||
| 2022-04-28 | crypto:starfive: disable crypto default on fpga. | william.qiu | 1 | -0/+1 | |
| For most fpga bitfile has no crypto, so disable it for better linux boot. Signed-off-by: william.qiu <william.qiu@starfivetech.com> | |||||
| 2022-04-28 | clk:starfive: Add isp clock tree driver | xingyu.wu | 1 | -0/+10 | |
| Clock references refer to include/dt-bindings/clock/starfive-jh7110-isp.h Enable the isp clock tree driver in dts file if use it. If the fpga is not connetted with isp board, the isp clock tree must be disabled. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> | |||||
| 2022-04-28 | dt-bingings:GPU: add clk/rst single | shanlong.li | 1 | -2/+13 | |
| add clk/rst single Signed-off-by: shanlong.li <shanlong.li@starfivetech.com> | |||||
| 2022-04-28 | Merge branch 'CR_846_FPGA-V1.0-VOUT_update_keith.zhao' into ↵ | andy.hu | 3 | -21/+318 | |
| 'jh7110_fpga_dev_5.15' riscv:linux:driver:DC8200 See merge request sdk/sft-riscvpi-linux-5.10!33 | |||||
| 2022-04-28 | defconfig: add crypto defconfig support. | william.qiu | 1 | -0/+3 | |
| add defconfig for jh7110 crypto. Signed-off-by: william.qiu <william.qiu@starfivetech.com> | |||||
| 2022-04-28 | dt-bingings:crypto: add crypto node for jh7110 soc. | william.qiu | 1 | -0/+34 | |
| add support for jh7110 crypto. Signed-off-by: william.qiu <william.qiu@starfivetech.com> | |||||
| 2022-04-27 | v4l2: add isp clk tree support | changhuang.liang | 1 | -10/+21 | |
| v4l2: delete isp top clk configure riscv:dts:starfive: vin add isp clk handle Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com> | |||||
| 2022-04-27 | riscv:linux:driver:DC8200 | keith.zhao | 3 | -21/+318 | |
| for DC8200 drm driver,update clk reset pinctrl and syscon api Signed-off-by: keith.zhao<keith.zhao@statfivetech.com> | |||||
| 2022-04-26 | v4l2: mipi channel add reset control suppurt | changhuang.liang | 1 | -10/+15 | |
| 2022-04-26 | v4l2: external modules resource use ioremap | changhuang.liang | 1 | -4/+4 | |
| 2022-04-26 | v4l2: sc2235 sensor use pinctrl set power | changhuang.liang | 2 | -8/+94 | |
| 2022-04-26 | v4l2: add sys clk tree support | changhuang.liang | 1 | -0/+3 | |
| 2022-04-26 | v4l2: add reset control support | changhuang.liang | 1 | -0/+11 | |
| 2022-04-26 | dts: modify sc2235 name | changhuang.liang | 1 | -1/+1 | |
| 2022-04-26 | v4l2: add pinctrl support | changhuang.liang | 2 | -1/+9 | |
| 2022-04-26 | v4l2: fixed sys_crg ioremap error! | changhuang.liang | 1 | -3/+2 | |
| 2022-04-26 | dt-bingings:e24: add e24 devicetree, use clk/rst/syscon. | shanlong.li | 2 | -0/+33 | |
| add e24 devicetree, use clk/rst/syscon. Signed-off-by: shanlong.li <shanlong.li@starfivetech.com> | |||||
| 2022-04-25 | dt-bingings:mailbox: Add clk/rst single. | shanlong.li | 1 | -0/+4 | |
| Add clk/rst single for mailbox. Signed-off-by: shanlong.li <shanlong.li@starfivetech.com> | |||||
| 2022-04-25 | Merge branch 'CR_854_RTC_hal.feng' into 'jh7110_fpga_dev_5.15' | andy.hu | 1 | -1/+6 | |
| rtc: starfive: Use stardand clock and reset apis for initialization See merge request sdk/sft-riscvpi-linux-5.10!30 | |||||
| 2022-04-25 | Merge branch 'CR_853_TRNG_hal.feng' into 'jh7110_fpga_dev_5.15' | andy.hu | 1 | -1/+4 | |
| Cr 853 trng hal.feng See merge request sdk/sft-riscvpi-linux-5.10!29 | |||||
| 2022-04-25 | Merge branch 'CR_871_PWM_hal.feng' into 'jh7110_fpga_dev_5.15' | andy.hu | 2 | -3/+10 | |
| Cr 871 pwm hal.feng See merge request sdk/sft-riscvpi-linux-5.10!28 | |||||
| 2022-04-25 | rtc: starfive: Use stardand clock and reset apis for initialization | Hal Feng | 1 | -1/+6 | |
| Signed-off-by: Hal Feng <hal.feng@starfivetech.com> | |||||
| 2022-04-25 | Merge branch 'CR_786_CAN_clivia.cai' into 'jh7110_fpga_dev_5.15' | andy.hu | 3 | -21/+17 | |
| Cr 786 can clivia.cai See merge request sdk/sft-riscvpi-linux-5.10!24 | |||||
| 2022-04-25 | Merge branch 'CR_886_I2C_hal.feng' into 'jh7110_fpga_dev_5.15' | andy.hu | 2 | -0/+18 | |
| riscv: dts: starfive: Add clock and reset for i2c See merge request sdk/sft-riscvpi-linux-5.10!27 | |||||
| 2022-04-25 | riscv: dts: starfive: Add clock and reset for i2c | Hal Feng | 2 | -0/+18 | |
| Signed-off-by: Hal Feng <hal.feng@starfivetech.com> | |||||
| 2022-04-24 | hw_random: starfive-trng: Use stardand clock and reset apis for initialization | Hal Feng | 1 | -1/+4 | |
| Signed-off-by: Hal Feng <hal.feng@starfivetech.com> | |||||
| 2022-04-24 | pwm: pwm-starfive-ptc: Use standard clock, reset, pinctrl framework for ↵ | Hal Feng | 2 | -2/+9 | |
| initialization Signed-off-by: Hal Feng <hal.feng@starfivetech.com> | |||||
| 2022-04-24 | riscv: dts: starfive: Fix string mismatch problem of ptc (pwm) | Hal Feng | 1 | -2/+2 | |
| Signed-off-by: Hal Feng <hal.feng@starfivetech.com> | |||||
| 2022-04-24 | risv:dts:starfive:Add timer clocktree | xingyu.wu | 4 | -4/+28 | |
| 1.Modify the clock tree driver to make timer clock ignore disabled_unused. 2.Add different 'clock-frequency' node in fpga, evb and visionfive dts file. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com> | |||||
| 2022-04-24 | Merge branch 'CR_865_GMAC_yanhong.wang' into 'jh7110_fpga_dev_5.15' | andy.hu | 2 | -7/+62 | |
| Cr 865 gmac yanhong.wang See merge request sdk/sft-riscvpi-linux-5.10!23 | |||||
| 2022-04-24 | dt-bingings:can:Add syscon register config | Clivia.Cai | 1 | -16/+12 | |
| Add the syscon register config for can/canfd dt-bindings. In addition, Redefine some attribute names. Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com> | |||||
| 2022-04-24 | dt-bingings:can:Modify reference | Clivia.Cai | 2 | -5/+5 | |
| Modify the reference of ipmscanx to canx Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com> | |||||
| 2022-04-24 | riscv: dts: jh7110: Fix syscon indentation issue | mason.huo | 1 | -6/+6 | |
| Remove additional tabs of syscon configurations. Signed-off-by: mason.huo <mason.huo@starfivetech.com> | |||||
| 2022-04-24 | PCI: plda: Add syscon register config | mason.huo | 1 | -0/+2 | |
| Add the syscon register config when plda hw initializes. Signed-off-by: mason.huo <mason.huo@starfivetech.com> | |||||
| 2022-04-24 | PCI: plda: Add pcie clk & rst | mason.huo | 1 | -2/+26 | |
| Signed-off-by: mason.huo <mason.huo@starfivetech.com> | |||||
| 2022-04-24 | PCI: plda: Add port1 support | mason.huo | 1 | -3/+27 | |
| Add configuration to support plda pcie port1. Signed-off-by: mason.huo <mason.huo@starfivetech.com> | |||||
| 2022-04-24 | dt-bingings:gmac:jh7110: add clk and reset signals for gmac | yanhong.wang | 2 | -7/+62 | |
| Gmac uses the Clock and reset framework API. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com> | |||||
| 2022-04-24 | Merge branch 'CR_881_DMA_curry.zhang' into 'jh7110_fpga_dev_5.15' | andy.hu | 1 | -1/+6 | |
| [DMA] : Add standard system clock tree & reset API See merge request sdk/sft-riscvpi-linux-5.10!22 | |||||
| 2022-04-24 | Merge branch 'CR_876_BoardTypeDef_Xingyu.Wu' into 'jh7110_fpga_dev_5.15' | andy.hu | 1 | -23/+0 | |
| Cr 876 board type def xingyu.wu See merge request sdk/sft-riscvpi-linux-5.10!18 | |||||
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |