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2021-08-04arm64: dts: qcom: pm660l: Support SPMI regulators on PMIC sid 3AngeloGioacchino Del Regno1-0/+4
The PM660L PMIC has SPMI regulators on the PMIC SID 3: let's add the compatible in order to probe them. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-23-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: pm660l: Add WLED supportKonrad Dybcio1-0/+17
This will enable backlight control on WLED-enabled devices. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-22-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: pm660: Support SPMI regulators on PMIC sid 1AngeloGioacchino Del Regno1-0/+11
The PM660 PMIC has SPMI regulators on the PMIC SID 1: let's declare the second pmic subtree and add the spmi vregs compatible to probe them there. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-21-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add Adreno 508 GPU configurationAngeloGioacchino Del Regno1-1/+83
The SDM630 SoC features an Adreno 508.0 GPU with a minimum frequency of 160MHz and a maximum of (depending on the speed-bin) 775MHz. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-20-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Raise tcsr_mutex_regs sizeKonrad Dybcio1-1/+1
Enlarge the size to make sure all relevant registers can be reached. This will be required to support the modem. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-19-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add ADSP remoteproc configurationKonrad Dybcio1-0/+83
Configure the ADSP remote processor and add a simple sound{} node to make way for future development. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-18-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add thermal-zones configurationKonrad Dybcio1-0/+173
Add a basic thermal-zones configuration to make sure the SoC doesn't overheat itself to death. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-17-konrad.dybcio@somainline.org [bjorn: Sorted thermal-zones below "soc"] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add modem/ADSP SMP2P nodesKonrad Dybcio1-0/+40
Add SMP2P nodes that are required for ADSP and modem bringup. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-16-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add TSENS nodeKonrad Dybcio1-0/+11
This will enable temperature reporting for various SoC components. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-15-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add qcom,adreno-smmu compatibleAngeloGioacchino Del Regno1-1/+2
The Adreno SMMU in SDM630 needs this compatible string for proper context handling and split pagetables support. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-14-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add clocks and power domains to SMMU nodesAngeloGioacchino Del Regno1-3/+28
Add the required clocks and power domains for the SMMUs to work. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-13-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add GPU Clock Controller nodeAngeloGioacchino Del Regno1-0/+17
Add the GPU Clock Controller in SDM630 and keep it disabled by default. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-12-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add interconnect and opp table to sdhc_1AngeloGioacchino Del Regno1-0/+28
The SDHC port 1 has interconnects and can make use of DVFS: define the interconnections and the OPP table in order to optimize performance and power consumption. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-11-konrad.dybcio@somainline.org [bjorn: Dropped "sdhc1-" prefix from opp-table node] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add SDHCI2 nodeAngeloGioacchino Del Regno1-0/+50
This will enable usage of (generally) uSD cards. While at it, add accompanying OPP table for DVFS. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-10-konrad.dybcio@somainline.org [bjorn: Dropped "sdhci1-" prefix from opp-table node] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Fix TLMM node and pinctrl configurationAngeloGioacchino Del Regno1-73/+139
Previous pinctrl configuration was wrong. Fix it and clean up how multi-pin states are described. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-9-konrad.dybcio@somainline.org [bjorn: Polished the commit message] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add USB configurationKonrad Dybcio1-0/+64
This will let us use USB2 on our devices. The SoC supposedly supports USB3, but there are no known cases of devices that actually have USB3 wired up in hardware. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-8-konrad.dybcio@somainline.org [bjorn: Changes dwc3 node name to "usb"] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add qfprom subnodesAngeloGioacchino Del Regno1-0/+10
These will be required for USB and Adreno support. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-7-konrad.dybcio@somainline.org [bjorn: y/_/-/ in gpu_speed_bin] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add MDSS nodesKonrad Dybcio1-2/+196
Add MDSS node along with its children to enable display functionality. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-6-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add interconnect provider nodesKonrad Dybcio1-0/+59
Add interconnect provider nodes to allow for NoC bus scaling. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-5-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add MMCC nodeKonrad Dybcio1-0/+28
Add MultiMedia Clock Controller node to allow for accessing and controlling Multimedia Subsystem clocks by their respective users. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-4-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add RPMPD nodesKonrad Dybcio1-0/+47
Add the rpmpd node on the sdm630 and define the available levels. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Rewrite memory mapAngeloGioacchino Del Regno1-23/+18
The memory map was wrong. Fix it. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sm8150: Fix incorrect cpu opp table entryThara Gopinath1-1/+1
CPU0 frequency 768MHz is wrongly modeled as 576000000 hz in cpu0_opp_table. Use the correct value 768000000 hz. Fixes: 2b6187abafea ("arm64: dts: qcom: sm8150: Add CPU opp tables") Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210804132847.2503269-1-thara.gopinath@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sm8150-mtp: Add 8150 compatible stringThara Gopinath1-1/+1
Add "qcom,sm8150" as one of the platform compatible strings. This will be later used by cpufreq-dt-platdev to exclude using cpufreq-dt cpufreq driver. Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210804133223.2503517-1-thara.gopinath@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: defconfig: Enable Qualcomm MSM8996 CPU clock driverBjorn Andersson1-0/+1
The MSM8996 supports CPU frequency scaling, so enable the clock driver for this. Acked-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210804193042.1155398-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm: dts: mt7623: increase passive cooling tripFrank Wunderlich1-1/+1
MT7623/BPI-R2 has idle temperature after bootup from 48 degrees celsius increase the passive trip temp threshold to not trottle CPU frequency at this temperature Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20210725163451.217610-1-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-08-04arm64: efi: Export screen_infoMichael Kelley1-0/+1
The Hyper-V frame buffer driver may be built as a module, and it needs access to screen_info. So export screen_info. Signed-off-by: Michael Kelley <mikelley@microsoft.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Marc Zyngier <maz@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/1628092359-61351-5-git-send-email-mikelley@microsoft.com Signed-off-by: Wei Liu <wei.liu@kernel.org>
2021-08-04arm64: hyperv: Initialize hypervisor on bootMichael Kelley2-1/+88
Add ARM64-specific code to initialize the Hyper-V hypervisor when booting as a guest VM. This code is built only when CONFIG_HYPERV is enabled. Signed-off-by: Michael Kelley <mikelley@microsoft.com> Acked-by: Marc Zyngier <maz@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/1628092359-61351-4-git-send-email-mikelley@microsoft.com Signed-off-by: Wei Liu <wei.liu@kernel.org>
2021-08-04arm64: hyperv: Add panic handlerMichael Kelley1-0/+52
Add a function to inform Hyper-V about a guest panic. This code is built only when CONFIG_HYPERV is enabled. Signed-off-by: Michael Kelley <mikelley@microsoft.com> Reviewed-by: Sunil Muthuswamy <sunilmut@microsoft.com> Reviewed-by: Boqun Feng <boqun.feng@gmail.com> Acked-by: Marc Zyngier <maz@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/1628092359-61351-3-git-send-email-mikelley@microsoft.com Signed-off-by: Wei Liu <wei.liu@kernel.org>
2021-08-04arm64: hyperv: Add Hyper-V hypercall and register access utilitiesMichael Kelley5-0/+255
hyperv-tlfs.h defines Hyper-V interfaces from the Hyper-V Top Level Functional Spec (TLFS), and #includes the architecture-independent part of hyperv-tlfs.h in include/asm-generic. The published TLFS is distinctly oriented to x86/x64, so the ARM64-specific hyperv-tlfs.h includes information for ARM64 that is not yet formally published. The TLFS is available here: docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs mshyperv.h defines Linux-specific structures and routines for interacting with Hyper-V on ARM64, and #includes the architecture- independent part of mshyperv.h in include/asm-generic. Use these definitions to provide utility functions to make Hyper-V hypercalls and to get and set Hyper-V provided registers associated with a virtual processor. Signed-off-by: Michael Kelley <mikelley@microsoft.com> Reviewed-by: Sunil Muthuswamy <sunilmut@microsoft.com> Acked-by: Marc Zyngier <maz@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/1628092359-61351-2-git-send-email-mikelley@microsoft.com Signed-off-by: Wei Liu <wei.liu@kernel.org>
2021-08-04riscv: Enable GENERIC_IRQ_SHOW_LEVELKefeng Wang1-0/+1
The interrupt controllers on riscv support both edge and level triggered interrupts, it's useful to provide that information in /proc/interrupts. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-08-04riscv: Enable idle generic idle loopKefeng Wang1-0/+1
Enable generic idle loop to support for hlt/nohlt command line options to override default idle loop behavior. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-08-04riscv: Allow forced irq threadingKefeng Wang1-0/+1
The timer interrupt and the perf interrupt on riscv are with IRQF_PERCPU, so it's safe to allow forced interrupt threading. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-08-04Merge tag 'at91-soc-5.15' of ↵Arnd Bergmann9-289/+950
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/soc AT91 soc for 5.15: - add new SoC based on a Cortex-A7 core: the SAMA7G5 family - mach-at91 entry, Kconfig and header files - Power Management Controller (PMC) code and associated power management changes. Support for suspend/resume, Ultra Low Power modes and Backup with Memory in Self-Refresh mode. - Power management association with DDR controller and shutdown controller for addressing this variety of modes. * tag 'at91-soc-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: (26 commits) ARM: at91: pm: add sama7g5 shdwc ARM: at91: pm: add pm support for SAMA7G5 ARM: at91: sama7: introduce sama7 SoC family ARM: at91: pm: add sama7g5's pmc ARM: at91: pm: add backup mode support for SAMA7G5 ARM: at91: pm: save ddr phy calibration data to securam ARM: at91: pm: add sama7g5 ddr phy controller ARM: at91: pm: add sama7g5 ddr controller ARM: at91: pm: wait for ddr power mode off ARM: at91: pm: add support for 2.5V LDO regulator control ARM: at91: pm: add support for MCK1..4 save/restore for ulp modes ARM: at91: pm: add self-refresh support for sama7g5 ARM: at91: ddr: add registers definitions for sama7g5's ddr ARM: at91: sfrbu: add sfrbu registers definitions for sama7g5 ARM: at91: pm: add support for waiting MCK1..4 ARM: at91: pm: s/CONFIG_SOC_SAM9X60/CONFIG_HAVE_AT91_SAM9X60_PLL/g ARM: at91: pm: avoid push and pop on stack while memory is in self-refersh ARM: at91: pm: use r7 instead of tmp1 ARM: at91: pm: do not initialize pdev ARM: at91: pm: check for different controllers in at91_pm_modes_init() ... Link: https://lore.kernel.org/r/20210804084316.12641-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-04KVM: SVM: improve the code readability for ASID managementMingwei Zhang1-19/+24
KVM SEV code uses bitmaps to manage ASID states. ASID 0 was always skipped because it is never used by VM. Thus, in existing code, ASID value and its bitmap postion always has an 'offset-by-1' relationship. Both SEV and SEV-ES shares the ASID space, thus KVM uses a dynamic range [min_asid, max_asid] to handle SEV and SEV-ES ASIDs separately. Existing code mixes the usage of ASID value and its bitmap position by using the same variable called 'min_asid'. Fix the min_asid usage: ensure that its usage is consistent with its name; allocate extra size for ASID 0 to ensure that each ASID has the same value with its bitmap position. Add comments on ASID bitmap allocation to clarify the size change. Signed-off-by: Mingwei Zhang <mizhang@google.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Marc Orr <marcorr@google.com> Cc: David Rientjes <rientjes@google.com> Cc: Alper Gun <alpergun@google.com> Cc: Dionna Glaze <dionnaglaze@google.com> Cc: Sean Christopherson <seanjc@google.com> Cc: Vipin Sharma <vipinsh@google.com> Cc: Peter Gonda <pgonda@google.com> Cc: Joerg Roedel <joro@8bytes.org> Message-Id: <20210802180903.159381-1-mizhang@google.com> [Fix up sev_asid_free to also index by ASID, as suggested by Sean Christopherson, and use nr_asids in sev_cpu_init. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-08-04perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guestLike Xu1-1/+2
If we use "perf record" in an AMD Milan guest, dmesg reports a #GP warning from an unchecked MSR access error on MSR_F15H_PERF_CTLx: [] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write 0x0000020000110076) at rIP: 0xffffffff8106ddb4 (native_write_msr+0x4/0x20) [] Call Trace: [] amd_pmu_disable_event+0x22/0x90 [] x86_pmu_stop+0x4c/0xa0 [] x86_pmu_del+0x3a/0x140 The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host, while the guest perf driver should avoid such use. Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled") Signed-off-by: Like Xu <likexu@tencent.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Liam Merwick <liam.merwick@oracle.com> Tested-by: Kim Phillips <kim.phillips@amd.com> Tested-by: Liam Merwick <liam.merwick@oracle.com> Link: https://lkml.kernel.org/r/20210802070850.35295-1-likexu@tencent.com
2021-08-04perf/x86: Fix out of bound MSR accessPeter Zijlstra1-5/+7
On Wed, Jul 28, 2021 at 12:49:43PM -0400, Vince Weaver wrote: > [32694.087403] unchecked MSR access error: WRMSR to 0x318 (tried to write 0x0000000000000000) at rIP: 0xffffffff8106f854 (native_write_msr+0x4/0x20) > [32694.101374] Call Trace: > [32694.103974] perf_clear_dirty_counters+0x86/0x100 The problem being that it doesn't filter out all fake counters, in specific the above (erroneously) tries to use FIXED_BTS. Limit the fixed counters indexes to the hardware supplied number. Reported-by: Vince Weaver <vincent.weaver@maine.edu> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Vince Weaver <vincent.weaver@maine.edu> Tested-by: Like Xu <likexu@tencent.com> Link: https://lkml.kernel.org/r/YQJxka3dxgdIdebG@hirez.programming.kicks-ass.net
2021-08-04Merge tag 'at91-dt-5.15' of ↵Arnd Bergmann13-21/+2191
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt AT91 dt for 5.15: - add sama7g5 SoC and associated evaluation kit, the sama7g5-ek - adaptation of some DT for sama5d27 som1 ek, sama5d4 xplained and sama5d2 icp boards - fixes to gpio and shutdown controller nodes for all boards * tag 'at91-dt-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: at91: use the right property for shutdown controller ARM: dts: at91: sama5d2_icp: enable digital filter for I2C nodes ARM: dts: at91: sama5d4_xplained: change the key code of the gpio key ARM: dts: at91: add conflict note for d3 ARM: dts: at91: add pinctrl-{names, 0} for all gpios ARM: dts: at91: sama5d27_som1_ek: enable ADC node ARM: dts: at91: sama5d4_xplained: Remove spi0 node dt-bindings: atmel-sysreg: add bindings for sama7g5 ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek dt-bindings: ARM: at91: document sama7g5ek board Link: https://lore.kernel.org/r/20210804085000.13233-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-04Merge tag 'ux500-dts-v5.15-1' of ↵Arnd Bergmann15-15/+2438
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt Ux500 Device Tree updates for the v5.15 kernel cycle: - New device trees for these mobile phones: - Samsung Gavini - Samsung Codina - Samsung Kyle - Flag eMMC cards as non-SD non-SDIO to save time - Link USB PHY to USB controller in the device tree - Fix up the operating points to the actual clock frequencies * tag 'ux500-dts-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: dts: ux500: Adjust operating points to reality ARM: dts: ux500: Add a device tree for Kyle ARM: dts: ux500: Add devicetree for Codina ARM: dts: ux500: ab8500: Link USB PHY to USB controller node ARM: dts: ux500: Flag eMMCs as non-SDIO/SD ARM: dts: ux500: Add device tree for Samsung Gavini Link: https://lore.kernel.org/r/CACRpkdbjBv5ywZZD8rK07d5sLcHsG8o4iYD-3jHO=HLg6-nKnA@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-04KVM: arm64: Unregister HYP sections from kmemleak in protected modeMarc Zyngier1-0/+7
Booting a KVM host in protected mode with kmemleak quickly results in a pretty bad crash, as kmemleak doesn't know that the HYP sections have been taken away. This is specially true for the BSS section, which is part of the kernel BSS section and registered at boot time by kmemleak itself. Unregister the HYP part of the BSS before making that section HYP-private. The rest of the HYP-specific data is obtained via the page allocator or lives in other sections, none of which is subjected to kmemleak. Fixes: 90134ac9cabb ("KVM: arm64: Protect the .hyp sections from the host") Reviewed-by: Quentin Perret <qperret@google.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org # 5.13 Link: https://lore.kernel.org/r/20210802123830.2195174-3-maz@kernel.org
2021-08-04arm64: Move .hyp.rodata outside of the _sdata.._edata rangeMarc Zyngier1-2/+2
The HYP rodata section is currently lumped together with the BSS, which isn't exactly what is expected (it gets registered with kmemleak, for example). Move it away so that it is actually marked RO. As an added benefit, it isn't registered with kmemleak anymore. Fixes: 380e18ade4a5 ("KVM: arm64: Introduce a BSS section for use at Hyp") Suggested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org #5.13 Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20210802123830.2195174-2-maz@kernel.org
2021-08-04x86/hyperv: fix root partition faults when writing to VP assist page MSRPraveen Kumar2-20/+53
For root partition the VP assist pages are pre-determined by the hypervisor. The root kernel is not allowed to change them to different locations. And thus, we are getting below stack as in current implementation root is trying to perform write to specific MSR. [ 2.778197] unchecked MSR access error: WRMSR to 0x40000073 (tried to write 0x0000000145ac5001) at rIP: 0xffffffff810c1084 (native_write_msr+0x4/0x30) [ 2.784867] Call Trace: [ 2.791507] hv_cpu_init+0xf1/0x1c0 [ 2.798144] ? hyperv_report_panic+0xd0/0xd0 [ 2.804806] cpuhp_invoke_callback+0x11a/0x440 [ 2.811465] ? hv_resume+0x90/0x90 [ 2.818137] cpuhp_issue_call+0x126/0x130 [ 2.824782] __cpuhp_setup_state_cpuslocked+0x102/0x2b0 [ 2.831427] ? hyperv_report_panic+0xd0/0xd0 [ 2.838075] ? hyperv_report_panic+0xd0/0xd0 [ 2.844723] ? hv_resume+0x90/0x90 [ 2.851375] __cpuhp_setup_state+0x3d/0x90 [ 2.858030] hyperv_init+0x14e/0x410 [ 2.864689] ? enable_IR_x2apic+0x190/0x1a0 [ 2.871349] apic_intr_mode_init+0x8b/0x100 [ 2.878017] x86_late_time_init+0x20/0x30 [ 2.884675] start_kernel+0x459/0x4fb [ 2.891329] secondary_startup_64_no_verify+0xb0/0xbb Since the hypervisor already provides the VP assist pages for root partition, we need to memremap the memory from hypervisor for root kernel to use. The mapping is done in hv_cpu_init during bringup and is unmapped in hv_cpu_die during teardown. Signed-off-by: Praveen Kumar <kumarpraveen@linux.microsoft.com> Reviewed-by: Sunil Muthuswamy <sunilmut@microsoft.com> Link: https://lore.kernel.org/r/20210731120519.17154-1-kumarpraveen@linux.microsoft.com Signed-off-by: Wei Liu <wei.liu@kernel.org>
2021-08-04sock: allow reading and changing sk_userlocks with setsockoptPavel Tikhomirov4-0/+8
SOCK_SNDBUF_LOCK and SOCK_RCVBUF_LOCK flags disable automatic socket buffers adjustment done by kernel (see tcp_fixup_rcvbuf() and tcp_sndbuf_expand()). If we've just created a new socket this adjustment is enabled on it, but if one changes the socket buffer size by setsockopt(SO_{SND,RCV}BUF*) it becomes disabled. CRIU needs to call setsockopt(SO_{SND,RCV}BUF*) on each socket on restore as it first needs to increase buffer sizes for packet queues restore and second it needs to restore back original buffer sizes. So after CRIU restore all sockets become non-auto-adjustable, which can decrease network performance of restored applications significantly. CRIU need to be able to restore sockets with enabled/disabled adjustment to the same state it was before dump, so let's add special setsockopt for it. Let's also export SOCK_SNDBUF_LOCK and SOCK_RCVBUF_LOCK flags to uAPI so that using these interface one can reenable automatic socket buffer adjustment on their sockets. Signed-off-by: Pavel Tikhomirov <ptikhomirov@virtuozzo.com> Reviewed-by: Eric Dumazet <edumazet@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-04ARM: ep93xx: remove MaverickCrunch supportArnd Bergmann25-557/+4
The MaverickCrunch support for ep93xx never made it into glibc and was removed from gcc in its 4.8 release in 2012. It is now one of the last parts of arch/arm/ that fails to build with the clang integrated assembler, which is unlikely to ever want to support it. The two alternatives are to force the use of binutils/gas when building the crunch support, or to remove it entirely. According to Hartley Sweeten: "Martin Guy did a lot of work trying to get the maverick crunch working but I was never able to successfully use it for anything. It "kind" of works but depending on the EP93xx silicon revision there are still a number of hardware bugs that either give imprecise or garbage results. I have no problem with removing the kernel support for the maverick crunch." Unless someone else comes up with a good reason to keep it around, remove it now. This touches mostly the ep93xx platform, but removes a bit of code from ARM common ptrace and signal frame handling as well. If there are remaining users of MaverickCrunch, they can use LTS kernels for at least another five years before kernel support ends. Link: https://lore.kernel.org/linux-arm-kernel/20210802141245.1146772-1-arnd@kernel.org/ Link: https://lore.kernel.org/linux-arm-kernel/20210226164345.3889993-1-arnd@kernel.org/ Link: https://github.com/ClangBuiltLinux/linux/issues/1272 Link: https://gcc.gnu.org/legacy-ml/gcc/2008-03/msg01063.html Cc: "Martin Guy" <martinwguy@martinwguy@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-04KVM: SVM: Fix off-by-one indexing when nullifying last used SEV VMCBSean Christopherson1-1/+1
Use the raw ASID, not ASID-1, when nullifying the last used VMCB when freeing an SEV ASID. The consumer, pre_sev_run(), indexes the array by the raw ASID, thus KVM could get a false negative when checking for a different VMCB if KVM manages to reallocate the same ASID+VMCB combo for a new VM. Note, this cannot cause a functional issue _in the current code_, as pre_sev_run() also checks which pCPU last did VMRUN for the vCPU, and last_vmentry_cpu is initialized to -1 during vCPU creation, i.e. is guaranteed to mismatch on the first VMRUN. However, prior to commit 8a14fe4f0c54 ("kvm: x86: Move last_cpu into kvm_vcpu_arch as last_vmentry_cpu"), SVM tracked pCPU on its own and zero-initialized the last_cpu variable. Thus it's theoretically possible that older versions of KVM could miss a TLB flush if the first VMRUN is on pCPU0 and the ASID and VMCB exactly match those of a prior VM. Fixes: 70cd94e60c73 ("KVM: SVM: VMRUN should use associated ASID when SEV is enabled") Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-08-04KVM: x86/pmu: Introduce pmc->is_paused to reduce the call time of perf ↵Like Xu4-4/+8
interfaces Based on our observations, after any vm-exit associated with vPMU, there are at least two or more perf interfaces to be called for guest counter emulation, such as perf_event_{pause, read_value, period}(), and each one will {lock, unlock} the same perf_event_ctx. The frequency of calls becomes more severe when guest use counters in a multiplexed manner. Holding a lock once and completing the KVM request operations in the perf context would introduce a set of impractical new interfaces. So we can further optimize the vPMU implementation by avoiding repeated calls to these interfaces in the KVM context for at least one pattern: After we call perf_event_pause() once, the event will be disabled and its internal count will be reset to 0. So there is no need to pause it again or read its value. Once the event is paused, event period will not be updated until the next time it's resumed or reprogrammed. And there is also no need to call perf_event_period twice for a non-running counter, considering the perf_event for a running counter is never paused. Based on this implementation, for the following common usage of sampling 4 events using perf on a 4u8g guest: echo 0 > /proc/sys/kernel/watchdog echo 25 > /proc/sys/kernel/perf_cpu_time_max_percent echo 10000 > /proc/sys/kernel/perf_event_max_sample_rate echo 0 > /proc/sys/kernel/perf_cpu_time_max_percent for i in `seq 1 1 10` do taskset -c 0 perf record \ -e cpu-cycles -e instructions -e branch-instructions -e cache-misses \ /root/br_instr a done the average latency of the guest NMI handler is reduced from 37646.7 ns to 32929.3 ns (~1.14x speed up) on the Intel ICX server. Also, in addition to collecting more samples, no loss of sampling accuracy was observed compared to before the optimization. Signed-off-by: Like Xu <likexu@tencent.com> Message-Id: <20210728120705.6855-1-likexu@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Peter Zijlstra <peterz@infradead.org>
2021-08-04KVM: X86: Optimize zapping rmapPeter Xu1-12/+29
Using rmap_get_first() and rmap_remove() for zapping a huge rmap list could be slow. The easy way is to travers the rmap list, collecting the a/d bits and free the slots along the way. Provide a pte_list_destroy() and do exactly that. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20210730220605.26377-1-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-08-04KVM: X86: Optimize pte_list_desc with per-array counterPeter Xu1-13/+22
Add a counter field into pte_list_desc, so as to simplify the add/remove/loop logic. E.g., we don't need to loop over the array any more for most reasons. This will make more sense after we've switched the array size to be larger otherwise the counter will be a waste. Initially I wanted to store a tail pointer at the head of the array list so we don't need to traverse the list at least for pushing new ones (if without the counter we traverse both the list and the array). However that'll need slightly more change without a huge lot benefit, e.g., after we grow entry numbers per array the list traversing is not so expensive. So let's be simple but still try to get as much benefit as we can with just these extra few lines of changes (not to mention the code looks easier too without looping over arrays). I used the same a test case to fork 500 child and recycle them ("./rmap_fork 500" [1]), this patch further speeds up the total fork time of about 4%, which is a total of 33% of vanilla kernel: Vanilla: 473.90 (+-5.93%) 3->15 slots: 366.10 (+-4.94%) Add counter: 351.00 (+-3.70%) [1] https://github.com/xzpeter/clibs/commit/825436f825453de2ea5aaee4bdb1c92281efe5b3 Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20210730220602.26327-1-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-08-04KVM: X86: MMU: Tune PTE_LIST_EXT to be biggerPeter Xu1-2/+2
Currently rmap array element only contains 3 entries. However for EPT=N there could have a lot of guest pages that got tens of even hundreds of rmap entry. A normal distribution of a 6G guest (even if idle) shows this with rmap count statistics: Rmap_Count: 0 1 2-3 4-7 8-15 16-31 32-63 64-127 128-255 256-511 512-1023 Level=4K: 3089171 49005 14016 1363 235 212 15 7 0 0 0 Level=2M: 5951 227 0 0 0 0 0 0 0 0 0 Level=1G: 32 0 0 0 0 0 0 0 0 0 0 If we do some more fork some pages will grow even larger rmap counts. This patch makes PTE_LIST_EXT bigger so it'll be more efficient for the general use case of EPT=N as we do list reference less and the loops over PTE_LIST_EXT will be slightly more efficient; but still not too large so less waste when array not full. It should not affecting EPT=Y since EPT normally only has zero or one rmap entry for each page, so no array is even allocated. With a test case to fork 500 child and recycle them ("./rmap_fork 500" [1]), this patch speeds up fork time of about 29%. Before: 473.90 (+-5.93%) After: 366.10 (+-4.94%) [1] https://github.com/xzpeter/clibs/commit/825436f825453de2ea5aaee4bdb1c92281efe5b3 Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20210730220455.26054-6-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-08-04ARM: imx_v6_v7_defconfig: Let CONFIG_SCSI_LOWLEVEL be selectedFabio Estevam1-1/+0
When using Yocto's Ptest DISTRO_FEATURE the CONFIG_SCSI_DEBUG=m option is added, but it cannot be selected as it depends on CONFIG_SCSI_LOWLEVEL. This generates a build warning saying that the CONFIG_SCSI_DEBUG=m option is discarded. Fix this by letting CONFIG_SCSI_LOWLEVEL to be selected. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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