summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)AuthorFilesLines
2015-10-27ARM: uniphier: rework SMP operations to use trampoline codeMasahiro Yamada3-31/+199
The complexity of the boot sequence of UniPhier SoC family is a PITA due to the following hardware limitations: [1] No dedicated on-chip SRAM SoCs in general have small SRAM, on which a tiny firmware or a boot loader can run before SDRAM is initialized. As UniPhier SoCs do not have any dedicated SRAM accessible from CPUs, the locked outer cache is used instead. Due to the ARM specification, to have access to the outer cache, the MMU must be enabled. This is done for all CPU cores by the program hard-wired in the boot ROM. The boot ROM code loads a small amount of program (this is usually SPL of U-Boot) from a non-volatile device onto the locked outer cache, and the primary CPU jumps to it. The secondary CPUs stay in the boot ROM until they are kicked by the primary CPU. [2] CPUs can not directly jump to SDRAM address space As mentioned above, the MMU is enable for all the CPUs with the page table hard-wired in the boot ROM. Unfortunately, the page table only has minimal sets of valid sections; all the sections of SDRAM address space are zero-filled. That means all the CPUs, including secondary ones, can not jump directly to SDRAM address space. So, the primary CPU must bring up secondary CPUs to accessible address mapped onto the outer cache, then again kick them to SDRAM address space. Before this commit, this complex task was done with help of a boot loader (U-Boot); U-Boot SPL brings up the secondary CPUs to the entry of U-Boot SPL and they stay there until they are kicked by Linux. This is not nice because a boot loader must put the secondary CPUs into a certain state expected by the kernel. It makes difficult to port another boot loader because the boot loader and the kernel must work in sync to wake up the secondary CPUs. This commit reworks the SMP operations so that they do not rely on particular boot loader implementation; the SMP operations (platsmp.c) put trampoline code (headsmp.S) on a locked way of the outer cache. The secondary CPUs jump from the boot ROM to secondary_entry via the trampoline code. The boot loader no longer needs to take care of SMP. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-27ARM: uniphier: add outer cache supportMasahiro Yamada5-0/+615
This commit adds support for UniPhier outer cache controller. All the UniPhier SoCs are equipped with the L2 cache, while the L3 cache is currently only integrated on PH1-Pro5 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-26Merge tag 'samsung-soc' of ↵Olof Johansson7-16/+41
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Samsung SoC updates for v4.4 - use PWM lookup table with pwm_add_table() for the following boards : s3c24xx h1940 and rx1950 : s3c64xx smdk6410, crag6410, hmt and smartq - document: update bootloader interface on exynos542x * tag 'samsung-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: Documentation: EXYNOS: Update bootloader interface on exynos542x ARM: S3C64XX: Use PWM lookup table for mach-smartq ARM: S3C64XX: Use PWM lookup table for mach-hmt ARM: S3C64XX: Use PWM lookup table for mach-crag6410 ARM: S3C64XX: Use PWM lookup table for smdk6410 ARM: S3C24XX: Use PWM lookup table for mach-rx1950 ARM: S3C24XX: Use PWM lookup table for mach-h1940 Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-26Merge tag 'mvebu-soc-4.4-2' of git://git.infradead.org/linux-mvebu into next/socOlof Johansson4-98/+36
mvebu soc for 4.4 (part 2) - Use mac_pton() helper in the oropn5x board instead of duplicating it - Add the broken-idle option allowing to boot boards with a mistake in the hardware design * tag 'mvebu-soc-4.4-2' of git://git.infradead.org/linux-mvebu: ARM: mvebu: add broken-idle option ARM: orion5x: use mac_pton() helper Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-26Merge tag 'tegra-for-4.4-soc' of ↵Olof Johansson1-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc ARM: tegra: Core SoC changes for v4.4-rc1 A single patch to restore rfkill support on AC100. * tag 'tegra-for-4.4-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: paz00: use con_id's to refer GPIO's in gpiod_lookup table Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-26Merge tag 'at91-ab-soc2' of ↵Olof Johansson1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into next/soc More SoC changes for 4.4: - a great fix for PM/suspend/resume * tag 'at91-ab-soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: ARM: at91: pm: at91_pm_suspend_in_sram() must be 8-byte aligned Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-23Merge tag 'imx-soc-4.4' of ↵Olof Johansson5-6/+127
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc The i.MX SoC updates for 4.4: - Enable suspend and cpufreq support for i.MX6UL - Add platform level ENET initialization support for i.MX7D * tag 'imx-soc-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx: add cpufreq device for imx6ul ARM: imx: add enet init for i.MX7D platform ARM: imx7d: add imx7d iomux-gpr field define ARM: imx: add suspend/resume support for i.mx6ul Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-23Merge tag 'v4.3-next-soc' of https://github.com/mbgg/linux-mediatek into ↵Olof Johansson3-0/+171
next/soc Do the initial setting of the pmic wrap interrupt before requesting the interrupt. This fixes the corner-case where the pmic is initialized by the bootloader, but not the pmic watchdog. Add support for active wakeup to the scpsys. This allows to keep the power of a scpsys domain during suspend state. With version v4.3 new subsystem clocks are added to the clock dirver. In late init the kernel turns off all unused clocks. This can provoke a hang if the kernel tries to access the venc and venc_lt power domain registers. Add the necessary parent clocks for this power domains to the scpsys so that no random hang happens. The bootloader of mt6589, mt8135 and mt1827 does not turn on the arm-arch-timer. As there is no opensource bootloader in the near future for this architectures we enable the arch timer at kernel boot. We need the arch timer for SMP boot. Add support for SMP on mt6589, mt8127 and mt8135. * tag 'v4.3-next-soc' of https://github.com/mbgg/linux-mediatek: ARM: mediatek: add smp bringup code ARM: mediatek: enable gpt6 on boot up to make arch timer working soc: mediatek: Fix random hang up issue while kernel init soc: mediatek: add scpsys support active_wakeup soc: mediatek: Move the initial setting of pmic wrap interrupt before requesting irq. Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-23Merge tag 'sunxi-core-for-4.4' of ↵Olof Johansson1-1/+2
https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/soc Allwinner core changes for 4.4 Add support for the Allwinner R8 SoC used in the CHIP. * tag 'sunxi-core-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: ARM: sunxi: Add R8 support Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-23ARM: mvebu: add broken-idle optionVincent Donnefort1-3/+26
The broken-idle option can be activated from the coherency-fabric DT node. This property allows to disable the idle capability, when the hardware doesn't support it, like the Seagate Personal Cloud boards. Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-10-23ARM: orion5x: use mac_pton() helperAndy Shevchenko3-95/+10
Instead of custom approach let's use generic helper function. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Detlef Vollmann <dv@vollmann.ch> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Tested-by: Detlef Vollmann <dv@vollmann.ch> #on DNS-323 Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-10-19ARM: at91: pm: at91_pm_suspend_in_sram() must be 8-byte alignedPatrick Doyle1-0/+2
fncpy() requires that the source and the destination are both 8-byte aligned. Signed-off-by: Patrick Doyle <pdoyle@irobot.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Fixes: d94e688cae56 ("ARM: at91/pm: move the copying the sram function to the sram initialization phase") Cc: <stable@vger.kernel.org> # 4.1+
2015-10-17ARM: sunxi: Add R8 supportMaxime Ripard1-1/+2
The R8 is a new Allwinner SoC based on the A13. While both are very similar, there's still a few differences. Introduce a new compatible to deal with them. In order to have a consistent naming, instead of mentioning the Allwinner A series as the machine name, switch to sun4i/sun5i like what is done for the other families. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-15Merge tag 'berlin-soc-for-4.4-2' of ↵Arnd Bergmann1-3/+35
git://git.infradead.org/users/hesselba/linux-berlin into next/soc Merge "Marvell Berlin SoC for 4.4 take 2" from Sebastian Hesselbarth: - use the non-self-clearing reset register - add cpu hotplug support * tag 'berlin-soc-for-4.4-2' of git://git.infradead.org/users/hesselba/linux-berlin: arm: berlin: add CPU hotplug support arm: berlin: use non-self-cleared reset register to reset cpu
2015-10-15ARM: digicolor: select pinctrl/gpio driverBaruch Siach1-0/+3
Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-10-15Merge tag 'arm-soc/for-4.4/soc' of http://github.com/Broadcom/stblinux into ↵Arnd Bergmann4-1/+53
next/soc Merge "Broadcom soc changes for v4.4 (try 2)" from Florian Fainelli: This pull request contains the following Broadcom SoC platform and driver changes: - Brian Norris create a drivers/soc/brcmstb/ stub as a place holder for SoC-specific code which is coming next - Florian Fainelli adds support for configuring the BCM7xxx SoCs Bus Interface Unit with their specific write-pairing setting, which must be saved and restored during system-wide suspend/resume, and consequently updates the brcmstb machine code to initialize the BIU - Jon Mason adds support for the Northstar Plus SoCs by introducing a custom machine descriptor matching their compatible string and setting up the PL310 L2 cache and enabling the relevant ARM errata for their Cortex-A9 * tag 'arm-soc/for-4.4/soc' of http://github.com/Broadcom/stblinux: ARM: brcmstb: Setup BIU control registers during boot soc: brcmstb: Add Bus Interface Unit control setup soc: add stubs for brcmstb SoC's ARM: NSP: Add basic support for Broadcom Northstar Plus SoC
2015-10-15Merge tag 'berlin-soc-for-4.4-1' of ↵Arnd Bergmann1-0/+6
git://git.infradead.org/users/hesselba/linux-berlin into next/soc Merge "Marvell SoC for 4.4 take 1" from Sebastian Hesselbarth: - register cpufreq-dt device * tag 'berlin-soc-for-4.4-1' of git://git.infradead.org/users/hesselba/linux-berlin: ARM: berlin: register cpufreq-dt
2015-10-15Merge tag 'berlin64-soc-for-4.4-1' of ↵Arnd Bergmann1-0/+1
git://git.infradead.org/users/hesselba/linux-berlin into next/soc Merge "Marvell Berlin ARM64 SoC for 4.4 take 1" from Sebastian Hesselbarth: - enable ARCH_REQUIRE_GPIOLIB for DW GPIO driver * tag 'berlin64-soc-for-4.4-1' of git://git.infradead.org/users/hesselba/linux-berlin: arm64: berlin: enable ARCH_REQUIRE_GPIOLIB
2015-10-15Merge tag 'mvebu-soc-4.4-1' of git://git.infradead.org/linux-mvebu into next/socArnd Bergmann1-0/+60
Merge "mvebu soc for 4.4 (part 1)" from Gregory CLEMENT: L2 caches optimization for Armada XP * tag 'mvebu-soc-4.4-1' of git://git.infradead.org/linux-mvebu: ARM: mvebu: add support to clear shared L2 bit on Armada XP
2015-10-15arm: berlin: add CPU hotplug supportJisheng Zhang1-0/+25
Add cpu hotplug support for berlin SoCs such as BG2 and BG2Q. These SoC don't support power off cpu independently, but we also want cpu hotplug support in these SoCs. We achieve this goal by putting the dying CPU in WFI state after the coherency is disabled, then asserting the dying CPU reset bit to put the CPU in reset state. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2015-10-15arm: berlin: use non-self-cleared reset register to reset cpuJisheng Zhang1-3/+10
In Berlin SoCs, there are two kinds of cpu reset control registers: the first one's corresponding bits will be self-cleared after some cycles, while the second one's bits won't. Previously the first kind of reset control register is used, this patch uses the second kind one to prepare for the next hotplug commit. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2015-10-14ARM: mediatek: add smp bringup codeYingjoe Chen2-0/+144
Add support for booting secondary CPUs on mt6589, mt8127 and mt8135. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-10-14ARM: mediatek: enable gpt6 on boot up to make arch timer workingMatthias Brugger1-0/+27
We enable GTP6 which ungates the arch timer clock. In the future this should be done in the bootloader. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
2015-10-12ARM: S3C64XX: Use PWM lookup table for mach-smartqThierry Reding1-2/+7
Use a PWM lookup table to provide the PWM to the pwm-backlight device. The driver has a legacy code path that is required only because boards still use the legacy method of requesting PWMs by global ID. Replacing these usages allows that legacy fallback to be removed. Signed-off-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-10-12ARM: S3C64XX: Use PWM lookup table for mach-hmtThierry Reding1-2/+7
Use a PWM lookup table to provide the PWM to the pwm-backlight device. The driver has a legacy code path that is required only because boards still use the legacy method of requesting PWMs by global ID. Replacing these usages allows that legacy fallback to be removed. Signed-off-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-10-12ARM: S3C64XX: Use PWM lookup table for mach-crag6410Thierry Reding1-2/+7
Use a PWM lookup table to provide the PWM to the pwm-backlight device. The driver has a legacy code path that is required only because boards still use the legacy method of requesting PWMs by global ID. Replacing these usages allows that legacy fallback to be removed. Signed-off-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-10-12ARM: S3C64XX: Use PWM lookup table for smdk6410Thierry Reding2-5/+7
Use a PWM lookup table to provide the PWM to the pwm-backlight device. The driver has a legacy code path that is required only because boards still use the legacy method of requesting PWMs by global ID. Replacing these usages allows that legacy fallback to be removed. Signed-off-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-10-12ARM: S3C24XX: Use PWM lookup table for mach-rx1950Thierry Reding1-2/+6
Use a PWM lookup table to provide the PWM to the pwm-backlight device. The driver has a legacy code path that is required only because boards still use the legacy method of requesting PWMs by global ID. Replacing these usages allows that legacy fallback to be removed. Signed-off-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-10-12ARM: S3C24XX: Use PWM lookup table for mach-h1940Thierry Reding1-3/+7
Use a PWM lookup table to provide the PWM to the pwm-backlight device. The driver has a legacy code path that is required only because boards still use the legacy method of requesting PWMs by global ID. Replacing these usages allows that legacy fallback to be removed. Signed-off-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-10-12ARM: imx: add cpufreq device for imx6ulBai Ping1-0/+7
Add cpufreq device for i.MX6UL. Using the common cpufreq of i.MX6 SOC. Signed-off-by: Bai Ping <b51503@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-10-09ARM: brcmstb: Setup BIU control registers during bootFlorian Fainelli1-0/+9
Call brcmstb_biuctrl_init() in brcmstb's init_irq machine descriptor callback since we need to setup the Bus Interface Unit before SMP in particular, but we also need to be able to remap registers. Acked-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-10-08ARM: meson: Enable Meson8b SoCsCarlo Caione2-0/+6
Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-10-06Merge tag 'at91-soc' of ↵Arnd Bergmann2-39/+20
git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/soc Merge "First little batch of SoC changes for 4.4" from Nicolas Ferre: - a MAINTAINER addition to cover SAMA5 SoCs - removal of one unneeded header file - for low-level serial output, use the DEBUG_UART_PHYS * tag 'at91-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: ARM: at91: debug: use DEBUG_UART_PHYS ARM: at91: remove useless includes in platform_data/atmel.h MAINTAINERS: explicitly add Atmel SAMA5
2015-10-06Merge tag 'renesas-soc-for-v4.4' of ↵Arnd Bergmann1-32/+3
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Merge "Renesas ARM Based SoC Updates for v4.4" from Simon Horman: * ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers This part of a multi-stage effort by Geert Uytterhoeven to add: "Clock Domain support to the Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks driver using the generic PM Domain, to be used on shmobile SoCs without device power domains (R-Car Gen1 and Gen2, RZ). This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume, similar to SoCs with device power domains (SH-Mobile and R-Mobile)." * tag 'renesas-soc-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers clk: shmobile: mstp: Consider "zb_clk" suitable for power management
2015-10-04Merge branch 'strscpy' of ↵Linus Torvalds22-29/+25
git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile Pull strscpy string copy function implementation from Chris Metcalf. Chris sent this during the merge window, but I waffled back and forth on the pull request, which is why it's going in only now. The new "strscpy()" function is definitely easier to use and more secure than either strncpy() or strlcpy(), both of which are horrible nasty interfaces that have serious and irredeemable problems. strncpy() has a useless return value, and doesn't NUL-terminate an overlong result. To make matters worse, it pads a short result with zeroes, which is a performance disaster if you have big buffers. strlcpy(), by contrast, is a mis-designed "fix" for strlcpy(), lacking the insane NUL padding, but having a differently broken return value which returns the original length of the source string. Which means that it will read characters past the count from the source buffer, and you have to trust the source to be properly terminated. It also makes error handling fragile, since the test for overflow is unnecessarily subtle. strscpy() avoids both these problems, guaranteeing the NUL termination (but not excessive padding) if the destination size wasn't zero, and making the overflow condition very obvious by returning -E2BIG. It also doesn't read past the size of the source, and can thus be used for untrusted source data too. So why did I waffle about this for so long? Every time we introduce a new-and-improved interface, people start doing these interminable series of trivial conversion patches. And every time that happens, somebody does some silly mistake, and the conversion patch to the improved interface actually makes things worse. Because the patch is mindnumbing and trivial, nobody has the attention span to look at it carefully, and it's usually done over large swatches of source code which means that not every conversion gets tested. So I'm pulling the strscpy() support because it *is* a better interface. But I will refuse to pull mindless conversion patches. Use this in places where it makes sense, but don't do trivial patches to fix things that aren't actually known to be broken. * 'strscpy' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: tile: use global strscpy() rather than private copy string: provide strscpy() Make asm/word-at-a-time.h available on all architectures
2015-10-04Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds13-144/+82
Pull MIPS updates from Ralf Baechle: "This week's round of MIPS fixes: - Fix JZ4740 build - Fix fallback to GFP_DMA - FP seccomp in case of ENOSYS - Fix bootmem panic - A number of FP and CPS fixes - Wire up new syscalls - Make sure BPF assembler objects can properly be disassembled - Fix BPF assembler code for MIPS I" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: scall: Always run the seccomp syscall filters MIPS: Octeon: Fix kernel panic on startup from memory corruption MIPS: Fix R2300 FP context switch handling MIPS: Fix octeon FP context switch handling MIPS: BPF: Fix load delay slots. MIPS: BPF: Do all exports of symbols with FEXPORT(). MIPS: Fix the build on jz4740 after removing the custom gpio.h MIPS: CPS: #ifdef on CONFIG_MIPS_MT_SMP rather than CONFIG_MIPS_MT MIPS: CPS: Don't include MT code in non-MT kernels. MIPS: CPS: Stop dangling delay slot from has_mt. MIPS: dma-default: Fix 32-bit fall back to GFP_DMA MIPS: Wire up userfaultfd and membarrier syscalls.
2015-10-04MIPS: scall: Always run the seccomp syscall filtersMarkos Chandras4-73/+42
The MIPS syscall handler code used to return -ENOSYS on invalid syscalls. Whilst this is expected, it caused problems for seccomp filters because the said filters never had the change to run since the code returned -ENOSYS before triggering them. This caused problems on the chromium testsuite for filters looking for invalid syscalls. This has now changed and the seccomp filters are always run even if the syscall is invalid. We return -ENOSYS once we return from the seccomp filters. Moreover, similar codepaths have been merged in the process which simplifies somewhat the overall syscall code. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11236/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-10-03Merge branch 'x86-urgent-for-linus' of ↵Linus Torvalds9-65/+69
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Ingo Molnar: "Fixes all around the map: W+X kernel mapping fix, WCHAN fixes, two build failure fixes for corner case configs, x32 header fix and a speling fix" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/headers/uapi: Fix __BITS_PER_LONG value for x32 builds x86/mm: Set NX on gap between __ex_table and rodata x86/kexec: Fix kexec crash in syscall kexec_file_load() x86/process: Unify 32bit and 64bit implementations of get_wchan() x86/process: Add proper bound checks in 64bit get_wchan() x86, efi, kasan: Fix build failure on !KASAN && KMEMCHECK=y kernels x86/hyperv: Fix the build in the !CONFIG_KEXEC_CORE case x86/cpufeatures: Correct spelling of the HWP_NOTIFY flag
2015-10-03Merge branch 'core-urgent-for-linus' of ↵Linus Torvalds2-2/+68
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull EFI fixes from Ingo Molnar: "Two EFI fixes: one for x86, one for ARM, fixing a boot crash bug that can trigger under newer EFI firmware" * 'core-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: arm64/efi: Fix boot crash by not padding between EFI_MEMORY_RUNTIME regions x86/efi: Fix boot crash by mapping EFI memmap entries bottom-up at runtime, instead of top-down
2015-10-02Merge tag 'arm64-fixes' of ↵Linus Torvalds2-4/+22
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Catalin Marinas: - Fix for transparent huge page change_protection() logic which was inadvertently changing a huge pmd page into a pmd table entry. - Function graph tracer panic fix caused by the return_to_handler code corrupting the multi-regs function return value (composite types). * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: ftrace: fix function_graph tracer panic arm64: Fix THP protection change logic
2015-10-02Merge branch 'for-linus' of ↵Linus Torvalds16-14/+165
git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k Pull m68k updates from Geert Uytterhoeven: "Summary: - Fix for accidental modification of arguments of syscall functions - Wire up new syscalls - Update defconfigs" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k: m68k/defconfig: Update defconfigs for v4.3-rc1 m68k: Define asmlinkage_protect m68k: Wire up membarrier m68k: Wire up userfaultfd m68k: Wire up direct socket calls
2015-10-02MIPS: Octeon: Fix kernel panic on startup from memory corruptionMatt Bennett1-1/+1
During development it was found that a number of builds would panic during the kernel init process, more specifically in 'delayed_fput()'. The panic showed the kernel trying to access a memory address of '0xb7fdc00' while traversing the 'delayed_fput_list' structure. Comparing this memory address to the value of the pointer used on builds that did not panic confirmed that the pointer on crashing builds must have been corrupted at some stage earlier in the init process. By traversing the list earlier and earlier in the code it was found that 'plat_mem_setup()' was responsible for corrupting the list. Specifically the line: memory = cvmx_bootmem_phy_alloc(mem_alloc_size, __pa_symbol(&__init_end), -1, 0x100000, CVMX_BOOTMEM_FLAG_NO_LOCKING); Which would eventually call: cvmx_bootmem_phy_set_size(new_ent_addr, cvmx_bootmem_phy_get_size (ent_addr) - (desired_min_addr - ent_addr)); Where 'new_ent_addr'=0x4800000 (the address of 'delayed_fput_list') and the second argument (size)=0xb7fdc00 (the address causing the kernel panic). The job of this part of 'plat_mem_setup()' is to allocate chunks of memory for the kernel to use. At the start of each chunk of memory the size of the chunk is written, hence the value 0xb7fdc00 is written onto memory at 0x4800000, therefore the kernel panics when it goes back to access 'delayed_fput_list' later on in the initialisation process. On builds that were not crashing it was found that the compiler had placed 'delayed_fput_list' at 0x4800008, meaning it wasn't corrupted (but something else in memory was overwritten). As can be seen in the first function call above the code begins to allocate chunks of memory beginning from the symbol '__init_end'. The MIPS linker script (vmlinux.lds.S) however defines the .bss section to begin after '__init_end'. Therefore memory within the .bss section is allocated to the kernel to use (System.map shows 'delayed_fput_list' and other kernel structures to be in .bss). To stop the kernel panic (and the .bss section being corrupted) memory should begin being allocated from the symbol '_end'. Signed-off-by: Matt Bennett <matt.bennett@alliedtelesis.co.nz> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: aleksey.makarov@auriga.com Patchwork: https://patchwork.linux-mips.org/patch/11251/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-10-02MIPS: Fix R2300 FP context switch handlingPaul Burton1-27/+1
Commit 1a3d59579b9f ("MIPS: Tidy up FPU context switching") removed FP context saving from the asm-written resume function in favour of reusing existing code to perform the same task. However it only removed the FP context saving code from the r4k_switch.S implementation of resume. Remove it from the r2300_switch.S implementation too in order to prevent attempting to save the FP context twice, which would likely lead to an exception from the second save because the FPU had already been disabled by the first save. This patch has only been build tested, using rbtx49xx_defconfig. Fixes: 1a3d59579b9f ("MIPS: Tidy up FPU context switching") Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: Manuel Lauss <manuel.lauss@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/11167/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-10-02MIPS: Fix octeon FP context switch handlingPaul Burton1-25/+1
Commit 1a3d59579b9f ("MIPS: Tidy up FPU context switching") removed FP context saving from the asm-written resume function in favour of reusing existing code to perform the same task. However it only removed the FP context saving code from the r4k_switch.S implementation of resume. Octeon uses its own implementation in octeon_switch.S, so remove FP context saving there too in order to prevent attempting to save context twice. That formerly led to an exception from the second save as follows because the FPU had already been disabled by the first save: do_cpu invoked from kernel context![#1]: CPU: 0 PID: 2 Comm: kthreadd Not tainted 4.3.0-rc2-dirty #2 task: 800000041f84a008 ti: 800000041f864000 task.ti: 800000041f864000 $ 0 : 0000000000000000 0000000010008ce1 0000000000100000 ffffffffbfffffff $ 4 : 800000041f84a008 800000041f84ac08 800000041f84c000 0000000000000004 $ 8 : 0000000000000001 0000000000000000 0000000000000000 0000000000000001 $12 : 0000000010008ce3 0000000000119c60 0000000000000036 800000041f864000 $16 : 800000041f84ac08 800000000792ce80 800000041f84a008 ffffffff81758b00 $20 : 0000000000000000 ffffffff8175ae50 0000000000000000 ffffffff8176c740 $24 : 0000000000000006 ffffffff81170300 $28 : 800000041f864000 800000041f867d90 0000000000000000 ffffffff815f3fa0 Hi : 0000000000fa8257 Lo : ffffffffe15cfc00 epc : ffffffff8112821c resume+0x9c/0x200 ra : ffffffff815f3fa0 __schedule+0x3f0/0x7d8 Status: 10008ce2 KX SX UX KERNEL EXL Cause : 1080002c (ExcCode 0b) PrId : 000d0601 (Cavium Octeon+) Modules linked in: Process kthreadd (pid: 2, threadinfo=800000041f864000, task=800000041f84a008, tls=0000000000000000) Stack : ffffffff81604218 ffffffff815f7e08 800000041f84a008 ffffffff811681b0 800000041f84a008 ffffffff817e9878 0000000000000000 ffffffff81770000 ffffffff81768340 ffffffff81161398 0000000000000001 0000000000000000 0000000000000000 ffffffff815f4424 0000000000000000 ffffffff81161d68 ffffffff81161be8 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ffffffff8111e16c 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ... Call Trace: [<ffffffff8112821c>] resume+0x9c/0x200 [<ffffffff815f3fa0>] __schedule+0x3f0/0x7d8 [<ffffffff815f4424>] schedule+0x34/0x98 [<ffffffff81161d68>] kthreadd+0x180/0x198 [<ffffffff8111e16c>] ret_from_kernel_thread+0x14/0x1c Tested using cavium_octeon_defconfig on an EdgeRouter Lite. Fixes: 1a3d59579b9f ("MIPS: Tidy up FPU context switching") Reported-by: Aaro Koskinen <aaro.koskinen@nokia.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-kernel@vger.kernel.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com> Cc: David Daney <david.daney@cavium.com> Cc: Leonid Rosenboim <lrosenboim@caviumnetworks.com> Patchwork: https://patchwork.linux-mips.org/patch/11166/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-10-02ARM: tegra: paz00: use con_id's to refer GPIO's in gpiod_lookup tableDmitry Osipenko1-2/+2
Commit 72daceb9a10a ("net: rfkill: gpio: Add default GPIO driver mappings for ACPI") removed possibility to request GPIO by table index for non-ACPI platforms without changing its users. As result "shutdown" GPIO request will fail if request for "reset" GPIO succeeded or "reset" will be requested instead of "shutdown" if "reset" wasn't defined. Fix it by making gpiod_lookup_table use con_id's instead of indexes. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Fixes: 72daceb (net: rfkill: gpio: Add default GPIO driver mappings for ACPI) Cc: <stable@vger.kernel.org> # v3.19+ Acked-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Marc Dietrich <marvin24@gmx.de> Tested-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-02arm64: ftrace: fix function_graph tracer panicLi Bin1-2/+20
When function graph tracer is enabled, the following operation will trigger panic: mount -t debugfs nodev /sys/kernel echo next_tgid > /sys/kernel/tracing/set_ftrace_filter echo function_graph > /sys/kernel/tracing/current_tracer ls /proc/ ------------[ cut here ]------------ [ 198.501417] Unable to handle kernel paging request at virtual address cb88537fdc8ba316 [ 198.506126] pgd = ffffffc008f79000 [ 198.509363] [cb88537fdc8ba316] *pgd=00000000488c6003, *pud=00000000488c6003, *pmd=0000000000000000 [ 198.517726] Internal error: Oops: 94000005 [#1] SMP [ 198.518798] Modules linked in: [ 198.520582] CPU: 1 PID: 1388 Comm: ls Tainted: G [ 198.521800] Hardware name: linux,dummy-virt (DT) [ 198.522852] task: ffffffc0fa9e8000 ti: ffffffc0f9ab0000 task.ti: ffffffc0f9ab0000 [ 198.524306] PC is at next_tgid+0x30/0x100 [ 198.525205] LR is at return_to_handler+0x0/0x20 [ 198.526090] pc : [<ffffffc0002a1070>] lr : [<ffffffc0000907c0>] pstate: 60000145 [ 198.527392] sp : ffffffc0f9ab3d40 [ 198.528084] x29: ffffffc0f9ab3d40 x28: ffffffc0f9ab0000 [ 198.529406] x27: ffffffc000d6a000 x26: ffffffc000b786e8 [ 198.530659] x25: ffffffc0002a1900 x24: ffffffc0faf16c00 [ 198.531942] x23: ffffffc0f9ab3ea0 x22: 0000000000000002 [ 198.533202] x21: ffffffc000d85050 x20: 0000000000000002 [ 198.534446] x19: 0000000000000002 x18: 0000000000000000 [ 198.535719] x17: 000000000049fa08 x16: ffffffc000242efc [ 198.537030] x15: 0000007fa472b54c x14: ffffffffff000000 [ 198.538347] x13: ffffffc0fada84a0 x12: 0000000000000001 [ 198.539634] x11: ffffffc0f9ab3d70 x10: ffffffc0f9ab3d70 [ 198.540915] x9 : ffffffc0000907c0 x8 : ffffffc0f9ab3d40 [ 198.542215] x7 : 0000002e330f08f0 x6 : 0000000000000015 [ 198.543508] x5 : 0000000000000f08 x4 : ffffffc0f9835ec0 [ 198.544792] x3 : cb88537fdc8ba316 x2 : cb88537fdc8ba306 [ 198.546108] x1 : 0000000000000002 x0 : ffffffc000d85050 [ 198.547432] [ 198.547920] Process ls (pid: 1388, stack limit = 0xffffffc0f9ab0020) [ 198.549170] Stack: (0xffffffc0f9ab3d40 to 0xffffffc0f9ab4000) [ 198.582568] Call trace: [ 198.583313] [<ffffffc0002a1070>] next_tgid+0x30/0x100 [ 198.584359] [<ffffffc0000907bc>] ftrace_graph_caller+0x6c/0x70 [ 198.585503] [<ffffffc0000907bc>] ftrace_graph_caller+0x6c/0x70 [ 198.586574] [<ffffffc0000907bc>] ftrace_graph_caller+0x6c/0x70 [ 198.587660] [<ffffffc0000907bc>] ftrace_graph_caller+0x6c/0x70 [ 198.588896] Code: aa0003f5 2a0103f4 b4000102 91004043 (885f7c60) [ 198.591092] ---[ end trace 6a346f8f20949ac8 ]--- This is because when using function graph tracer, if the traced function return value is in multi regs ([x0-x7]), return_to_handler may corrupt them. So in return_to_handler, the parameter regs should be protected properly. Cc: <stable@vger.kernel.org> # 3.18+ Signed-off-by: Li Bin <huawei.libin@huawei.com> Acked-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-10-02MIPS: BPF: Fix load delay slots.Ralf Baechle1-0/+4
The entire bpf_jit_asm.S is written in noreorder mode because "we know better" according to a comment. This also prevented the assembler from throwing in the required NOPs for MIPS I processors which have no load-use interlock, thus the load's consumer might end up using the old value of the register from prior to the load. Fixed by putting the assembler in reorder mode for just the affected load instructions. This is not enough for gas to actually try to be clever by looking at the next instruction and inserting a nop only when needed but as the comment said "we know better", so getting gas to unconditionally emit a NOP is just right in this case and prevents adding further ifdefery. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-10-02x86/headers/uapi: Fix __BITS_PER_LONG value for x32 buildsBen Hutchings1-1/+1
On x32, gcc predefines __x86_64__ but long is only 32-bit. Use __ILP32__ to distinguish x32. Fixes this compiler error in perf: tools/include/asm-generic/bitops/__ffs.h: In function '__ffs': tools/include/asm-generic/bitops/__ffs.h:19:8: error: right shift count >= width of type [-Werror=shift-count-overflow] word >>= 32; ^ This isn't sufficient to build perf for x32, though. Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mike Galbraith <efault@gmx.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Link: http://lkml.kernel.org/r/1443660043.2730.15.camel@decadent.org.uk Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-10-02x86/mm: Set NX on gap between __ex_table and rodataStephen Smalley1-1/+1
Unused space between the end of __ex_table and the start of rodata can be left W+x in the kernel page tables. Extend the setting of the NX bit to cover this gap by starting from text_end rather than rodata_start. Before: ---[ High Kernel Mapping ]--- 0xffffffff80000000-0xffffffff81000000 16M pmd 0xffffffff81000000-0xffffffff81600000 6M ro PSE GLB x pmd 0xffffffff81600000-0xffffffff81754000 1360K ro GLB x pte 0xffffffff81754000-0xffffffff81800000 688K RW GLB x pte 0xffffffff81800000-0xffffffff81a00000 2M ro PSE GLB NX pmd 0xffffffff81a00000-0xffffffff81b3b000 1260K ro GLB NX pte 0xffffffff81b3b000-0xffffffff82000000 4884K RW GLB NX pte 0xffffffff82000000-0xffffffff82200000 2M RW PSE GLB NX pmd 0xffffffff82200000-0xffffffffa0000000 478M pmd After: ---[ High Kernel Mapping ]--- 0xffffffff80000000-0xffffffff81000000 16M pmd 0xffffffff81000000-0xffffffff81600000 6M ro PSE GLB x pmd 0xffffffff81600000-0xffffffff81754000 1360K ro GLB x pte 0xffffffff81754000-0xffffffff81800000 688K RW GLB NX pte 0xffffffff81800000-0xffffffff81a00000 2M ro PSE GLB NX pmd 0xffffffff81a00000-0xffffffff81b3b000 1260K ro GLB NX pte 0xffffffff81b3b000-0xffffffff82000000 4884K RW GLB NX pte 0xffffffff82000000-0xffffffff82200000 2M RW PSE GLB NX pmd 0xffffffff82200000-0xffffffffa0000000 478M pmd Signed-off-by: Stephen Smalley <sds@tycho.nsa.gov> Acked-by: Kees Cook <keescook@chromium.org> Cc: <stable@vger.kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mike Galbraith <efault@gmx.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Link: http://lkml.kernel.org/r/1443704662-3138-1-git-send-email-sds@tycho.nsa.gov Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-10-02x86/kexec: Fix kexec crash in syscall kexec_file_load()Lee, Chun-Yi1-4/+3
The original bug is a page fault crash that sometimes happens on big machines when preparing ELF headers: BUG: unable to handle kernel paging request at ffffc90613fc9000 IP: [<ffffffff8103d645>] prepare_elf64_ram_headers_callback+0x165/0x260 The bug is caused by us under-counting the number of memory ranges and subsequently not allocating enough ELF header space for them. The bug is typically masked on smaller systems, because the ELF header allocation is rounded up to the next page. This patch modifies the code in fill_up_crash_elf_data() by using walk_system_ram_res() instead of walk_system_ram_range() to correctly count the max number of crash memory ranges. That's because the walk_system_ram_range() filters out small memory regions that reside in the same page, but walk_system_ram_res() does not. Here's how I found the bug: After tracing prepare_elf64_headers() and prepare_elf64_ram_headers_callback(), the code uses walk_system_ram_res() to fill-in crash memory regions information to the program header, so it counts those small memory regions that reside in a page area. But, when the kernel was using walk_system_ram_range() in fill_up_crash_elf_data() to count the number of crash memory regions, it filters out small regions. I printed those small memory regions, for example: kexec: Get nr_ram ranges. vaddr=0xffff880077592258 paddr=0x77592258, sz=0xdc0 Based on the code in walk_system_ram_range(), this memory region will be filtered out: pfn = (0x77592258 + 0x1000 - 1) >> 12 = 0x77593 end_pfn = (0x77592258 + 0xfc0 -1 + 1) >> 12 = 0x77593 end_pfn - pfn = 0x77593 - 0x77593 = 0 <=== if (end_pfn > pfn) is FALSE So, the max_nr_ranges that's counted by the kernel doesn't include small memory regions - causing us to under-allocate the required space. That causes the page fault crash that happens in a later code path when preparing ELF headers. This bug is not easy to reproduce on small machines that have few CPUs, because the allocated page aligned ELF buffer has more free space to cover those small memory regions' PT_LOAD headers. Signed-off-by: Lee, Chun-Yi <jlee@suse.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Baoquan He <bhe@redhat.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mike Galbraith <efault@gmx.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Takashi Iwai <tiwai@suse.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vivek Goyal <vgoyal@redhat.com> Cc: kexec@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: <stable@vger.kernel.org> Link: http://lkml.kernel.org/r/1443531537-29436-1-git-send-email-jlee@suse.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-17 20:38:34 +0300