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2022-06-13DRM: use CONFIG_DRM_STARFIVE_MIPI_DSI change display channelVF_SDK_510_V1.1.2changhuang.liang1-1/+1
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13dts/starfive: fixed v4l2 conflictchanghuang.liang2-3/+4
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13V4l2: add v4l2 drivers support!changhuang.liang3-0/+278
dts/starfive: add v4l2 configure! Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13drivers/reset: add isp reset support!changhuang.liang1-0/+7
drivers/reset: modify reset-starfive-jh7100.c dts/satrfive: add isp resst support! Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13drivers/clk: add isp clk support!changhuang.liang1-0/+10
dts/starfive: add isp clk configure! Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabledVincent1-1/+1
The errata_cip_453.o should be built only when the Kconfig CONFIG_ERRATA_SIFIVE_CIP_453 is enabled. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Vincent <vincent.chen@sifive.com> Fixes: 0e0d4992517f ("riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y") Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2022-06-13riscv: sifive: Apply errata "cip-1200" patchVincent Chen4-2/+40
For certain SiFive CPUs, "sfence.vma addr" cannot exactly flush addr from TLB in the particular cases. The details could be found here: https://sifive.cdn.prismic.io/sifive/167a1a56-03f4-4615-a79e-b2a86153148f_FU740_errata_20210205.pdf In order to ensure the functionality, this patch uses the Alternative scheme to replace all "sfence.vma addr" with "sfence.vma" at runtime. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2022-06-13riscv: sifive: Apply errata "cip-453" patchVincent Chen6-3/+94
Add sign extension to the $badaddr before addressing the instruction page fault and instruction access fault to workaround the issue "cip-453". To avoid affecting the existing code sequence, this patch will creates two trampolines to add sign extension to the $badaddr. By the "alternative" mechanism, these two trampolines will replace the original exception handler of instruction page fault and instruction access fault in the excp_vect_table. In this case, only the specific SiFive CPU core jumps to the do_page_fault and do_trap_insn_fault through these two trampolines. Other CPUs are not affected. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2022-06-13riscv: sifive: Add SiFive alternative portsVincent Chen7-0/+89
Add required ports of the Alternative scheme for SiFive. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2022-06-13riscv: Introduce alternative mechanism to apply errata solutionVincent Chen14-0/+301
Introduce the "alternative" mechanism from ARM64 and x86 to apply the CPU vendors' errata solution at runtime. The main purpose of this patch is to provide a framework. Therefore, the implementation is quite basic for now so that some scenarios could not use this schemei, such as patching code to a module, relocating the patching code and heterogeneous CPU topology. Users could use the macro ALTERNATIVE to apply an errata to the existing code flow. In the macro ALTERNATIVE, users need to specify the manufacturer information(vendorid, archid, and impid) for this errata. Therefore, kernel will know this errata is suitable for which CPU core. During the booting procedure, kernel will select the errata required by the CPU core and then patch it. It means that the kernel only applies the errata to the specified CPU core. In this case, the vendor's errata does not affect each other at runtime. The above patching procedure only occurs during the booting phase, so we only take the overhead of the "alternative" mechanism once. This "alternative" mechanism is enabled by default to ensure that all required errata will be applied. However, users can disable this feature by the Kconfig "CONFIG_RISCV_ERRATA_ALTERNATIVE". Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2022-06-13riscv: Add 3 SBI wrapper functions to get cpu manufacturer informationVincent Chen2-0/+18
Add 3 wrapper functions to get vendor id, architecture id and implement id from M-mode Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2022-06-13drm: fixed conflict errorchanghuang.liang1-6/+0
2022-06-13dts/starfive: drm config default hdmichanghuang.liang1-1/+1
2022-06-13DRM: fixed drm register before i2c controllerchanghuang.liang2-14/+26
DRM: fixed hdmi color problem Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: add clk and reset apichanghuang.liang2-21/+29
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: add drm driver supportchanghuang.liang2-145/+196
dts/starfive: add drm driver configure Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13dts:starfive:Release Audio devices nodesxingyu.wu2-11/+4
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-06-13Support AC108 daughter board for 3 dev-boardsWalkerChenL3-1/+9
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-06-13riscv: dts: starfive: Support AC108 daughter boardWalkerChenL4-1/+49
Add device tree support for AC108 daughter board, using the clock generated by Clock Tree. Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-06-13RISC-V: Add StarFive JH7100 audio reset nodeEmil Renner Berthing1-6/+6
Add device tree node for the audio resets on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13RISC-V: Add StarFive JH7100 audio clock nodeEmil Renner Berthing1-10/+10
Add device tree node for the audio clocks on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-05-27pinctrl: starfive: Add mutex to lockVF_SDK_510_V1.0.2Jianlong Huang1-0/+2
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-04-26add timer device and modify timer clk configjianlong.huang1-0/+21
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-21delete useless config to testjianlong.huang2-7/+9
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-21modify SOC_STARFIVE macro to SOC_STARFIVE_VIC7100jianlong.huang2-9/+1
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-21pwm: pwm-sifive-ptc: Use actual clock rateHal Feng1-2/+2
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-21riscv: dts: starfive: Modify devicee tree for JH7100WalkerChenL4-2/+66
Support WM8960 daughter board in 3 dev-boards by modifying device tree. Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-04-21modify clock tree and support i2s audioWalker Chen4-154/+220
2022-04-21riscv: dts: Add full JH7100, Starlight and VisionFive supportEmil Renner Berthing6-149/+1229
Based on the device tree in https://github.com/starfive-tech/u-boot/ with contributions from: yanhong.wang <yanhong.wang@starfivetech.com> Huan.Feng <huan.feng@starfivetech.com> ke.zhu <ke.zhu@starfivetech.com> yiming.li <yiming.li@starfivetech.com> jack.zhu <jack.zhu@starfivetech.com> Samin Guo <samin.guo@starfivetech.com> Chenjieqin <Jessica.Chen@starfivetech.com> bo.li <bo.li@starfivetech.com> Rearranged, cleanups, fixes, pins and resets added by Emil. Cleanups, fixes, clocks added by Geert. Cleanups and GPIO fixes from Drew. Thermal zone added by Stephen. PWM pins added by Jianlong. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Stephen L Arnold <nerdboy@gentoo.org> Signed-off-by: Drew Fustini <drew@beagleboard.org> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-04-21riscv: dts: starfive: Group tuples in interrupt propertiesGeert Uytterhoeven1-4/+4
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-04-21riscv: Add -ffreestanding for string functionsEmil Renner Berthing1-0/+6
The string library implements memset, memcpy and other library functions, so tell the compiler not to optimise such code to just calls to themselves. This is correct for all compilers, but for some reason only Clang builds break without this flag. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-04-21riscv: add ARCH_DMA_MINALIGN supportXianting Tian1-0/+2
Introduce ARCH_DMA_MINALIGN to riscv arch. Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com>
2022-04-21RISC-V: Add BeagleV Starlight Beta device treeEmil Renner Berthing2-2/+166
commit a43676272a6e0b398781bc5337ca4cc187ba923d upstream. Add initial device tree for the BeagleV Starlight Beta board. About 300 of these boards were sent out as part of a now cancelled BeagleBoard.org project. I2C timing data is based on the device tree in the vendor u-boot port. Heartbeat LED added by Geert. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Co-developed-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-04-21RISC-V: Add initial StarFive JH7100 device treeEmil Renner Berthing1-0/+230
commit ec85362fb121d0297b9f3bb56816ea6282c34fda upstream. Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. The CPU and cache data is based on the device tree in the vendor u-boot port. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-04-21RISC-V: Add StarFive SoC Kconfig optionEmil Renner Berthing1-0/+8
commit 3d24568b01c5a7a9e88f73f917477b60edb35bfe upstream. Add StarFive Kconfig option to select SoC specific and common drivers required for these SoCs. Select subsystems required to boot so the required drivers gets enabled by default. Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-04-18dts: moving the dts files from Uboot to kernelAndy Hu9-0/+1975
Keep the same dts file with Uboot vic_starlight branch which attach to the 5.10 kernel Signed-off-by: Andy Hu <andy.hu@starfivetech.com>
2021-03-09add the linux patch from 192.168.110.194 gitserverHuan.Feng1-36/+2905
2021-02-24[CONFIG] Add BCMDHD as module.Tom1-1/+17
2021-02-24[CONFIG] Make vic7100 device DesignWare SPI build in kernel.Tom1-1/+4
2021-02-24[CONFIG] Make vic7100 device PWM-PTC build in kernel.Tom1-2/+2
2021-02-24[CONFIG] Make vic7100 CDNS3 USB host build in kernel.Tom1-3/+5
2021-02-24add default config for fedora with sd and net support.Tom1-0/+8483
2021-02-24Add StarFive VIC7100 EVB default config with net&usb enabledTom1-0/+2691
2021-02-24Add StarFive VIC7100 EVB default config with net enabledTom1-0/+2516
2021-02-24Add StarFive VIC7100 EVB minimal config fileTom1-0/+2408
2021-02-24Add Starfive VIC7100 supportTom1-0/+58
2021-02-16riscv: Fixup CONFIG_GENERIC_TIME_VSYSCALLGuo Ren2-2/+2
The patch fix commit: ad5d112 ("riscv: use vDSO common flow to reduce the latency of the time-related functions"). The GENERIC_TIME_VSYSCALL should be CONFIG_GENERIC_TIME_VSYSCALL or vgettimeofday won't work. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Palmer Dabbelt <palmerdabbelt@google.com> Cc: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Pekka Enberg <penberg@kernel.org>
2021-02-16ARM: dts: pandaboard es: add bluetooth uart for HCIH. Nikolaus Schaller1-0/+32
The wl271 bluetooth uart is connected to uart2. Setup a serdev uart child and separate bluetooth and uart2 pinmux from wl12xx pinmux to better group the pins and muxes. Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-02-16update phy on pine64 a64 devicesPeter Robinson1-1/+1
2021-02-16arm64: dts: rockchip: disable USB type-c DisplayPortJian-Hong Pan1-1/+1
The cdn-dp sub driver probes the device failed on PINEBOOK Pro. kernel: cdn-dp fec00000.dp: [drm:cdn_dp_probe [rockchipdrm]] *ERROR* missing extcon or phy kernel: cdn-dp: probe of fec00000.dp failed with error -22 Then, the device halts all of the DRM related device jobs. For example, the operations: vop_component_ops, vop_component_ops and rockchip_dp_component_ops cannot be bound to corresponding devices. So, Xorg cannot find the correct DRM device. The USB type-C DisplayPort does not work for now. So, disable the DisplayPort node until the type-C phy work has been done. Link: https://patchwork.kernel.org/patch/11794141/#23639877 Signed-off-by: Jian-Hong Pan <jhp@endlessos.org>
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