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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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x86
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kernel
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tsc_msr.c
Age
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Author
Files
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2020-08-15
Merge tag 'x86-urgent-2020-08-15' of git://git.kernel.org/pub/scm/linux/kerne...
Linus Torvalds
1
-2
/
+7
2020-08-07
x86/tsr: Fix tsc frequency enumeration bug on Lightning Mountain SoC
Dilip Kota
1
-2
/
+7
2020-08-06
locking/seqlock, headers: Untangle the spaghetti monster
Peter Zijlstra
1
-0
/
+1
2020-03-31
Merge tag 'x86-timers-2020-03-30' of git://git.kernel.org/pub/scm/linux/kerne...
Linus Torvalds
1
-16
/
+112
2020-03-24
x86/kernel: Convert to new CPU match macros
Thomas Gleixner
1
-7
/
+7
2020-03-12
x86/tsc_msr: Make MSR derived TSC frequency more accurate
Hans de Goede
1
-11
/
+86
2020-03-12
x86/tsc_msr: Fix MSR_FSB_FREQ mask for Cherry Trail devices
Hans de Goede
1
-2
/
+15
2020-03-12
x86/tsc_msr: Use named struct initializers
Hans de Goede
1
-10
/
+18
2019-09-06
x86/cpu: Update init data for new Airmont CPU model
Rahul Tanwar
1
-0
/
+5
2019-05-09
x86/apic: Rename 'lapic_timer_frequency' to 'lapic_timer_period'
Daniel Drake
1
-2
/
+2
2018-10-02
x86/cpu: Sanitize FAM6_ATOM naming
Peter Zijlstra
1
-5
/
+5
2018-07-03
x86/platform/intel-mid: Remove custom TSC calibration
Andy Shevchenko
1
-0
/
+5
2018-07-03
x86/tsc: Use SPDX identifier and update Intel copyright
Andy Shevchenko
1
-4
/
+3
2018-07-03
x86/tsc: Convert to use x86_match_cpu() and INTEL_CPU_FAM6()
Andy Shevchenko
1
-41
/
+42
2018-07-03
x86/tsc: Add missing header to tsc_msr.c
Andy Shevchenko
1
-0
/
+1
2016-11-18
x86/tsc: Set TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Atom SoCs
Bin Gao
1
-0
/
+19
2016-07-11
x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration
Len Brown
1
-1
/
+1
2016-07-10
x86/tsc_msr: Add Airmont reference clock values
Len Brown
1
-1
/
+4
2016-07-10
x86/tsc_msr: Correct Silvermont reference clock values
Len Brown
1
-3
/
+3
2016-07-10
x86/tsc_msr: Update comments, expand definitions
Len Brown
1
-26
/
+10
2016-07-10
x86/tsc_msr: Remove debugging messages
Len Brown
1
-16
/
+3
2016-07-10
x86/tsc_msr: Identify Intel-specific code
Len Brown
1
-0
/
+3
2016-07-10
Revert "x86/tsc: Add missing Cherrytrail frequency to the table"
Len Brown
1
-3
/
+0
2016-05-12
x86/tsc: Add missing Cherrytrail frequency to the table
Jeremy Compostella
1
-0
/
+3
2016-05-06
x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO
Chen Yu
1
-1
/
+1
2014-02-19
x86: tsc: Add missing Baytrail frequency to the table
Mika Westerberg
1
-1
/
+1
2014-02-19
x86, tsc: Fallback to normal calibration if fast MSR calibration fails
Thomas Gleixner
1
-14
/
+14
2014-01-17
x86, tsc, apic: Unbreak static (MSR) calibration when CONFIG_X86_LOCAL_APIC=n
H. Peter Anvin
1
-0
/
+2
2014-01-16
x86, tsc: Add static (MSR) TSC calibration on Intel Atom SoCs
Bin Gao
1
-0
/
+125