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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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arch
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x86
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kernel
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cpu
/
hygon.c
Age
Commit message (
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Author
Files
Lines
2024-02-16
x86/cpu: Use common topology code for HYGON
Thomas Gleixner
1
-129
/
+0
2023-11-13
x86/barrier: Do not serialize MSR accesses on AMD
Borislav Petkov (AMD)
1
-0
/
+3
2023-10-31
Merge tag 'x86-core-2023-10-29-v2' of git://git.kernel.org/pub/scm/linux/kern...
Linus Torvalds
1
-19
/
+19
2023-10-10
x86/cpu: Move cpu_l[l2]c_id into topology info
Thomas Gleixner
1
-9
/
+5
2023-10-10
x86/cpu: Move cpu_core_id into topology info
Thomas Gleixner
1
-2
/
+2
2023-10-10
x86/cpu: Move cpu_die_id into topology info
Thomas Gleixner
1
-4
/
+4
2023-10-10
x86/cpu: Move phys_proc_id into topology info
Thomas Gleixner
1
-3
/
+3
2023-10-10
x86/cpu: Encapsulate topology information in cpuinfo_x86
Thomas Gleixner
1
-6
/
+6
2023-10-10
x86/cpu/hygon: Fix the CPU topology evaluation for real
Pu Wen
1
-2
/
+6
2023-09-22
x86/cpu: Clear SVM feature if disabled by BIOS
Paolo Bonzini
1
-0
/
+10
2023-08-09
x86/apic: Get rid of hard_smp_processor_id()
Thomas Gleixner
1
-1
/
+2
2022-12-14
Merge tag 'x86_cpu_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds
1
-1
/
+1
2022-11-22
x86/cpu: Switch to cpu_feature_enabled() for X86_FEATURE_XENPV
Juergen Gross
1
-1
/
+1
2022-11-15
x86/cpu: Restore AMD's DE_CFG MSR after resume
Borislav Petkov
1
-2
/
+2
2022-06-27
x86/cpu/amd: Add Spectral Chicken
Peter Zijlstra
1
-0
/
+6
2021-10-21
x86/cpu: Fix migration safety with X86_BUG_NULL_SEL
Jane Malalane
1
-0
/
+2
2021-06-01
perf/x86/rapl: Use CPUID bit on AMD and Hygon parts
Andrew Cooper
1
-0
/
+4
2021-03-06
x86/cpu/hygon: Set __max_die_per_package on Hygon
Pu Wen
1
-2
/
+2
2020-12-08
x86/cpu/amd: Remove dead code for TSEG region remapping
Arvind Sankar
1
-20
/
+0
2020-11-19
x86/CPU/AMD: Save AMD NodeId as cpu_die_id
Yazen Ghannam
1
-6
/
+5
2020-08-06
locking/seqlock, headers: Untangle the spaghetti monster
Peter Zijlstra
1
-0
/
+1
2019-07-22
x86: Remove X86_FEATURE_MFENCE_RDTSC
Josh Poimboeuf
1
-18
/
+3
2019-03-23
x86/CPU/hygon: Fix phys_proc_id calculation logic for multi-die processors
Pu Wen
1
-0
/
+5
2018-09-27
x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana
Pu Wen
1
-0
/
+3
2018-09-27
x86/cpu: Create Hygon Dhyana architecture support file
Pu Wen
1
-0
/
+405