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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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arch
/
x86
/
kernel
/
cpu
/
cacheinfo.c
Age
Commit message (
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)
Author
Files
Lines
2023-05-15
x86/cpu/cacheinfo: Remove cpu_callout_mask dependency
Thomas Gleixner
1
-4
/
+17
2023-02-11
x86/cacheinfo: Remove unused trace variable
Borislav Petkov (AMD)
1
-4
/
+1
2022-11-10
x86/cacheinfo: Switch cache_ap_init() to hotplug callback
Juergen Gross
1
-3
/
+15
2022-11-10
x86: Decouple PAT and MTRR handling
Juergen Gross
1
-1
/
+2
2022-11-10
x86/mtrr: Add a stop_machine() handler calling only cache_cpu_init()
Juergen Gross
1
-1
/
+58
2022-11-10
x86/mtrr: Let cache_aps_delayed_init replace mtrr_aps_delayed_init
Juergen Gross
1
-0
/
+12
2022-11-10
x86/mtrr: Disentangle MTRR init from PAT init
Juergen Gross
1
-0
/
+17
2022-11-10
x86/mtrr: Move cache control code to cacheinfo.c
Juergen Gross
1
-0
/
+77
2022-11-10
x86/mtrr: Replace use_intel() with a local flag
Juergen Gross
1
-0
/
+3
2022-07-18
x86/cacheinfo: move shared cache map definitions
Sander Vanheule
1
-0
/
+6
2021-10-15
sched: Add cluster scheduler level for x86
Tim Chen
1
-0
/
+1
2021-09-01
drivers: base: cacheinfo: Get rid of DEFINE_SMP_CALL_CACHE_FUNCTION()
Thomas Gleixner
1
-5
/
+2
2021-04-07
x86/cacheinfo: Remove unneeded dead-store initialization
Yang Li
1
-1
/
+1
2020-11-19
x86/CPU/AMD: Remove amd_get_nb_id()
Yazen Ghannam
1
-1
/
+1
2020-11-19
x86/CPU/AMD: Save AMD NodeId as cpu_die_id
Yazen Ghannam
1
-3
/
+3
2020-08-24
treewide: Use fallthrough pseudo-keyword
Gustavo A. R. Silva
1
-1
/
+1
2019-06-19
x86/cacheinfo: Fix a -Wtype-limits warning
Qian Cai
1
-2
/
+1
2019-01-26
x86/kernel: Mark expected switch-case fall-throughs
Gustavo A. R. Silva
1
-0
/
+1
2018-12-08
x86/kernel: Fix more -Wmissing-prototypes warnings
Borislav Petkov
1
-0
/
+1
2018-09-27
x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana
Pu Wen
1
-2
/
+29
2018-06-22
x86/CPU/AMD: Fix LLC ID bit-shift calculation
Suravee Suthikulpanit
1
-1
/
+1
2018-05-13
x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()
David Wang
1
-2
/
+3
2018-05-13
x86/CPU: Move cpu local function declarations to local header
Thomas Gleixner
1
-0
/
+2
2018-05-06
x86/CPU/AMD: Calculate last level cache ID from number of sharing threads
Suravee Suthikulpanit
1
-0
/
+39
2018-05-06
x86/CPU: Rename intel_cacheinfo.c to cacheinfo.c
Borislav Petkov
1
-0
/
+968