| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-11-13 | perf/x86/intel/pt: Prevent redundant WRMSRs | Alexander Shishkin | 1 | -3/+7 |
| 2019-11-13 | perf/x86/intel/pt: Opportunistically use single range output mode | Alexander Shishkin | 1 | -0/+2 |
| 2019-08-26 | perf/x86/intel/pt: Get rid of reverse lookup table for ToPA | Alexander Shishkin | 1 | -4/+6 |
| 2019-08-26 | perf/x86/intel/pt: Clean up ToPA allocation path | Alexander Shishkin | 1 | -2/+0 |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 | Thomas Gleixner | 1 | -9/+1 |
| 2018-12-21 | perf/x86/intel/pt: Export pt_cap_get() | Chao Peng | 1 | -21/+0 |
| 2018-12-21 | perf/x86/intel/pt: Move Intel PT MSRs bit defines to global header | Chao Peng | 1 | -37/+0 |
| 2017-03-30 | perf/x86/intel/pt: Allow the disabling of branch tracing | Alexander Shishkin | 1 | -0/+1 |
| 2017-03-16 | perf/core: Keep AUX flags in the output handle | Will Deacon | 1 | -1/+0 |
| 2016-09-20 | perf/x86/intel/pt: Add support for PTWRITE and power event tracing | Alexander Shishkin | 1 | -0/+5 |
| 2016-05-05 | perf/x86/intel/pt: Export CPU frequency ratios needed by PT decoders | Alexander Shishkin | 1 | -0/+6 |
| 2016-05-05 | perf/x86/intel/pt: Add support for address range filtering in PT | Alexander Shishkin | 1 | -0/+26 |
| 2016-05-05 | perf/x86/intel/pt: Add IP filtering register/CPUID bits | Alexander Shishkin | 1 | -0/+12 |
| 2016-05-05 | perf/x86/intel/pt: Move PT specific MSR bit definitions to a private header | Alexander Shishkin | 1 | -0/+24 |
| 2016-04-28 | perf/x86/intel/pt: Don't die on VMXON | Alexander Shishkin | 1 | -0/+3 |
| 2016-02-17 | perf/x86: Move perf_event_intel_pt.[ch] ...... => x86/events/intel/pt.[ch] | Borislav Petkov | 1 | -0/+116 |
