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2006-03-20[SPARC64]: Kill spurious semicolon in sun4v_pci_init().David S. Miller1-1/+1
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Program IRQ registers correctly on sun4v.David S. Miller1-24/+47
Need to use hypervisor calls instead of direct register accesses. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Generic sun4v_build_irq().David S. Miller2-28/+34
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: More SUN4V PCI work.David S. Miller1-14/+102
Get bus range from child of PCI controller root nexus. This is actually a hack, but the PCI-E bridge sitting at the top of the PCI tree responds to PCI config cycles for every device number, so best to just ignore it for now. Preliminary PCI irq routing, needs lots of work. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Implement rest of generic interrupt hypervisor calls.David S. Miller1-1/+65
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Move devino_to_sysino out of pci_sun4v_asm.SDavid S. Miller3-14/+12
It is not PCI specific, it is for all system interrupts. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Range check bus number in SUN4V PCI controller driver.David S. Miller1-9/+24
It has to be somewhere in the range from pbm->pci_first_busno to pbm->pci_last_busno, inclusive. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Missing 'return' statement in sun4v_pci_init().David S. Miller1-4/+3
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Implement basic pci_sun4v_scan_bus().David S. Miller1-3/+46
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: PCI-SUN4V fixes.David S. Miller1-8/+33
Clear top 8-bits of physical addresses in "ranges" property. This gives the actual physical address. Detect PBM-A vs. PBM-B by checking bit 0x40 of the devhandle. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Don't expect cfg space in PCI PBM ranges on SUN4V.David S. Miller1-15/+5
PCI cfg space is accessed transparently through the Hypervisor and not through direct cpu PIO operations. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Recognize "virtual-console" as input and output console device.David S. Miller1-0/+5
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Do not try to synchronize %stick registers on SUN4V.David S. Miller1-1/+5
Writes by privileged code are not allowed. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Do not try to write to %tick or %stick on SUN4V.David S. Miller1-10/+16
Writes by privileged code are disallowed. The hypervisor manages the non-privileged bit. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix mondo queue allocations.David S. Miller3-30/+59
We have to use bootmem during init_IRQ and page alloc for sibling cpu calls. Also, fix incorrect hypervisor call return value checks in the hypervisor SMP cpu mondo send code. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Deal with PTE layout differences in SUN4V.David S. Miller5-291/+11
Yes, you heard it right, they changed the PTE layout for SUN4V. Ho hum... This is the simple and inefficient way to support this. It'll get optimized, don't worry. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Register kernel TSB with hypervisor.David S. Miller1-1/+3
We do this right after we take over the trap table from OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix some SUN4V TLB miss bugs.David S. Miller2-13/+68
Code patching did not sign extend negative branch offsets correctly. Kernel TLB miss path needs patching and %g4 register preservation in order to handle SUN4V correctly. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix typo in sun4v_patch().David S. Miller1-1/+1
Second instruction offset is '4' not '3'. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix sun4v early bootup.David S. Miller1-15/+20
prom_sun4v_name should be "sun4v" not "SUNW,sun4v" Also, this is too early to make use of the .sun4v_Xinsn_patch code patching, so just check things manually. This gets us at least to prom_init() on Niagara. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fetch bootup time of day from Hypervisor.David S. Miller1-8/+50
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Simplify sun4v TLB handling using macros.David S. Miller2-87/+61
There was also a bug in sun4v_itlb_miss, it loaded the MMU Fault Status base into %g3 instead of %g2. This pointed out a fast path for TSB miss processing, since we have %g2 with the MMU Fault Status base, we can use that to quickly load up the PGD phys address. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.David S. Miller4-141/+107
This is where the virtual address of the fault status area belongs. To set it up we don't make a hypervisor call, instead we call OBP's SUNW,set-trap-table with the real address of the fault status area as the second argument. And right before that call we write the virtual address into ASI_SCRATCHPAD vaddr 0x0. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: First cut at SUN4V PCI IOMMU handling.David S. Miller4-31/+550
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix hypervisor call arg passing.David S. Miller4-43/+43
Function goes in %o5, args go in %o0 --> %o5. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Implement SUN4V PCI config space access.David S. Miller3-4/+93
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: More SUN4V PCI controller work.David S. Miller4-1/+364
Add assembler file for PCI hypervisor calls. Setup basic skeleton of SUN4V PCI controller driver. Add 32-bit devhandle to PBM struct, as this is needed for hypervisor calls. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Beginnings of SUN4V PCI controller support.David S. Miller4-9/+107
Abstract out IOMMU operations so that we can have a different set of calls on sun4v, which needs to do things through hypervisor calls. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fetch cpu mid properly on sun4v.David S. Miller1-3/+20
If there is a "cpuid" property, use that. Else suck it out of the top bits of the "reg" property. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: SUN4V memory exception trap handlers.David S. Miller4-24/+325
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Hypervisor TSB context switching.David S. Miller1-15/+27
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Implement sun4v TSB miss handlers.David S. Miller3-9/+64
When we register a TSB with the hypervisor, so that it or hardware can handle TLB misses and do the TSB walk for us, the hypervisor traps down to these trap when it incurs a TSB miss. Processing is simple, we load the missing virtual address and context, and do a full page table walk. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: kernel/cpu.c needs asm/spitfire.hDavid S. Miller1-0/+1
For 'tlb_type'. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Print ARCH as SUN4V when tlb_type is hypervisor.David S. Miller1-1/+4
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Detect sun4v early in boot process.David S. Miller7-53/+204
We look for "SUNW,sun4v" in the 'compatible' property of the root OBP device tree node. Protect every %ver register access, to make sure it is not touched on sun4v, as %ver is hyperprivileged there. Lock kernel TLB entries using hypervisor calls instead of calls into OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Sun4v cross-call sending support.David S. Miller3-2/+151
Technically the hypervisor call supports sending in a list of all cpus to get the cross-call, but I only pass in one cpu at a time for now. The multi-cpu support is there, just ifdef'd out so it's easy to enable or delete it later. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Sun4v interrupt handling.David S. Miller5-3/+554
Sun4v has 4 interrupt queues: cpu, device, resumable errors, and non-resumable errors. A set of head/tail offset pointers help maintain a work queue in physical memory. The entries are 64-bytes in size. Each queue is allocated then registered with the hypervisor as we bring cpus up. The two error queues each get a kernel side buffer that we use to quickly empty the main interrupt queue before we call up to C code to log the event and possibly take evasive action. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Allocate and register the 4 sun4v mondo queues at bootup.David S. Miller2-1/+59
Needs to occur before we enable PSTATE_IE in %pstate. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Verify all trap_per_cpu assembler offsets in trap_init()David S. Miller1-1/+12
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Patch up mmu context register writes for sun4v.David S. Miller6-41/+166
sun4v uses ASI_MMU instead of ASI_DMMU Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Register per-cpu fault status area with sun4v hypervisor.David S. Miller1-0/+3
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Niagara copy/clear page.David S. Miller1-0/+18
Happily we have no D-cache aliasing issues on these chips, so the implementation is very straightforward. Add a stub in bootup which will be where the patching calls will be made for niagara/sun4v/hypervisor. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patchDavid S. Miller6-26/+26
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Initial sun4v TLB miss handling infrastructure.David S. Miller5-15/+309
Things are a little tricky because, unlike sun4u, we have to: 1) do a hypervisor trap to do the TLB load. 2) do the TSB lookup calculations by hand Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Add missing memory barriers to instruction patching functions.David S. Miller1-0/+7
V9 requires a write memory barrier before the instruction flush. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Sanitize %pstate writes for sun4v.David S. Miller4-10/+49
If we're just switching between different alternate global sets, nop it out on sun4v. Also, get rid of all of the alternate global save/restore in the OBP CIF trampoline code. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Kill all %pstate changes in context switch code.David S. Miller1-1/+4
They are totally unnecessary because: 1) Interrupts are already disabled when switch_to() runs. 2) We don't use hard-coded alternate globals any longer. This found a case in rtrap, which still assumed alternate global %g6 was current_thread_info(), and that is fixed by this changeset as well. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Add initial code to twiddle %gl on trap entry/exit.David S. Miller4-3/+53
Instead of setting/clearing PSTATE_AG we have to change the %gl register value on sun4v. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fill dead cycles on trap entry with real work.David S. Miller1-12/+15
As we save trap state onto the stack, the store buffer fills up mid-way through and we stall for several cycles as the store buffer trickles out to the L2 cache. Meanwhile we can do some privileged register reads and other calculations, essentially for free. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Add sun4v case to __GET_CPUID() patch tables.David S. Miller1-0/+3
Signed-off-by: David S. Miller <davem@davemloft.net>
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