| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2009-10-09 | sparc64: Fix niagara2 perf IRQ bits. | David S. Miller | 1 | -1/+1 |
| 2009-09-30 | sparc64: Cache per-cpu %pcr register value in perf code. | David S. Miller | 1 | -17/+42 |
| 2009-09-30 | sparc64: Fix comment typo in perf_event.c | David S. Miller | 1 | -1/+1 |
| 2009-09-29 | sparc64: Minor coding style fixups in perf code. | David S. Miller | 1 | -7/+5 |
| 2009-09-29 | sparc64: Add a basic conflict engine in preparation for multi-counter support. | David S. Miller | 1 | -5/+64 |
| 2009-09-28 | sparc64: Add initial perf event conflict resolution and checks. | David S. Miller | 1 | -5/+77 |
| 2009-09-27 | sparc: Niagara1 perf event support. | David S. Miller | 1 | -0/+119 |
| 2009-09-27 | sparc: Add Niagara2 HW cache event support. | David S. Miller | 1 | -0/+88 |
| 2009-09-27 | sparc: Support all ultra3 and ultra4 derivatives. | David S. Miller | 1 | -10/+13 |
| 2009-09-27 | sparc: Support HW cache events. | David S. Miller | 1 | -6/+139 |
| 2009-09-21 | perf: Do the big rename: Performance Counters -> Performance Events | Ingo Molnar | 1 | -0/+556 |
 |
index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |