starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2017-11-29	RISC-V: Remove smb_mb__{before,after}_spinlock()	Palmer Dabbelt	1	-8/+0
2017-11-29	RISC-V: Remove __smp_bp__{before,after}_atomic	Palmer Dabbelt	1	-15/+0
2017-11-29	RISC-V: Comment on why {,cmp}xchg is ordered how it is	Palmer Dabbelt	1	-2/+7
2017-11-29	RISC-V: Remove unused arguments from ATOMIC_OP	Palmer Dabbelt	1	-47/+47
2017-11-27	RISC-V: Add VDSO entries for clock_get/gettimeofday/getcpu	Andrew Waterman	6	-1/+113
2017-11-27	RISC-V: Remove __vdso_cmpxchg{32,64} symbol versions	Palmer Dabbelt	1	-2/+0
2017-11-15	Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub...	Linus Torvalds	102	-0/+9776
2017-09-27	RISC-V: Build Infrastructure	Palmer Dabbelt	9	-0/+579
2017-09-27	RISC-V: User-facing API	Palmer Dabbelt	27	-0/+1687
2017-09-27	RISC-V: Paging and MMU	Palmer Dabbelt	8	-0/+1192
2017-09-27	RISC-V: Device, timer, IRQs, and the SBI	Palmer Dabbelt	9	-0/+566
2017-09-27	RISC-V: Task implementation	Palmer Dabbelt	9	-0/+1243
2017-09-27	RISC-V: ELF and module implementation	Palmer Dabbelt	4	-0/+187
2017-09-27	RISC-V: Generic library routines and assembly	Palmer Dabbelt	11	-0/+1389
2017-09-27	RISC-V: Atomic and Locking Code	Palmer Dabbelt	10	-0/+1423
2017-09-27	RISC-V: Init and Halt Code	Palmer Dabbelt	15	-0/+1524