starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2019-09-05	riscv: move the TLB flush logic out of line	Christoph Hellwig	2	-0/+38
2019-09-05	riscv: cleanup riscv_cpuid_to_hartid_mask	Christoph Hellwig	1	-1/+0
2019-08-30	RISC-V: Implement sparsemem	Logan Gunthorpe	1	-0/+10
2019-08-30	riscv: Using CSR numbers to access CSRs	Bin Meng	2	-7/+2
2019-07-18	Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...	Linus Torvalds	4	-68/+315
2019-07-09	RISC-V: Setup initial page tables in two stages	Anup Patel	1	-52/+255
2019-07-09	Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...	Linus Torvalds	1	-3/+3
2019-07-04	riscv: remove free_initrd_mem	Christoph Hellwig	1	-5/+0
2019-07-04	riscv: ccache: Remove unused variable	Yash Shah	1	-4/+7
2019-07-04	riscv: Introduce huge page support for 32/64bit kernel	Alexandre Ghiti	2	-0/+46
2019-07-01	RISC-V: Fix memory reservation in setup_bootmem()	Anup Patel	1	-7/+7
2019-06-27	riscv: mm: Fix code comment	ShihPo Hung	1	-3/+0
2019-06-17	Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/ke...	Linus Torvalds	1	-0/+13
2019-06-17	riscv: mm: synchronize MMU after pte change	ShihPo Hung	1	-0/+13
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	3	-27/+3
2019-05-29	signal/riscv: Remove tsk parameter from do_trap	Eric W. Biederman	1	-3/+3
2019-05-24	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120	Thomas Gleixner	2	-28/+2
2019-05-21	treewide: Add SPDX license identifier - Makefile/Kconfig	Thomas Gleixner	1	-0/+1
2019-05-19	Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	5	-6/+310
2019-05-17	riscv: fix locking violation in page fault handler	Andreas Schwab	1	-1/+2
2019-05-17	RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs	Yash Shah	2	-0/+176
2019-05-17	riscv: move switch_mm to its own file	Gary Guo	2	-0/+70
2019-05-17	riscv: move flush_icache_{all,mm} to cacheflush.c	Gary Guo	1	-0/+61
2019-05-17	RISC-V: Access CSRs using CSR numbers	Anup Patel	1	-5/+1
2019-05-14	riscv: switch over to generic free_initmem()	Mike Rapoport	1	-5/+0
2019-04-10	RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems	Anup Patel	1	-0/+8
2019-03-27	RISC-V: Always compile mm/init.c with cmodel=medany and notrace	Anup Patel	2	-0/+34
2019-02-21	RISC-V: Free-up initrd in free_initrd_mem()	Anup Patel	1	-1/+2
2019-02-21	RISC-V: Implement compile-time fixed mappings	Anup Patel	1	-0/+34
2019-02-21	RISC-V: Move setup_vm() to mm/init.c	Anup Patel	1	-0/+49
2019-02-21	RISC-V: Move setup_bootmem() to mm/init.c	Anup Patel	1	-0/+70
2019-01-24	riscv: fixup max_low_pfn with PFN_DOWN.	Guo Ren	1	-1/+2
2018-10-31	mm: remove include/linux/bootmem.h	Mike Rapoport	1	-2/+1
2018-10-31	memblock: rename free_all_bootmem to memblock_free_all	Mike Rapoport	1	-1/+1
2018-10-23	RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremap	Vincent Chen	1	-1/+1
2018-08-18	mm: convert return type of handle_mm_fault() caller to vm_fault_t	Souptick Joarder	1	-1/+2
2018-07-04	RISC-V: Add conditional macro for zone of DMA32	Zong Li	1	-0/+2
2018-02-07	Merge tag 'riscv-for-linus-4.16-merge_window' of git://git.kernel.org/pub/scm...	Linus Torvalds	2	-6/+10
2018-02-01	Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel...	Linus Torvalds	1	-1/+0
2018-01-31	riscv: rename sptbr to satp	Christoph Hellwig	1	-0/+4
2018-01-31	riscv: don't read back satp in paging_init	Christoph Hellwig	1	-2/+0
2018-01-31	riscv: add ZONE_DMA32	Christoph Hellwig	1	-4/+6
2018-01-08	riscv: rename SR_* constants to match the spec	Christoph Hellwig	1	-1/+1
2017-12-05	riscv: use linux/uaccess.h, not asm/uaccess.h...	Al Viro	1	-1/+0
2017-12-02	RISC-V: Fixes for clean allmodconfig build	Palmer Dabbelt	1	-1/+1
2017-11-30	RISC-V: Flush I$ when making a dirty page executable	Andrew Waterman	2	-0/+24
2017-11-30	RISC-V: io.h: type fixes for warnings	Olof Johansson	1	-1/+1
2017-09-27	RISC-V: Build Infrastructure	Palmer Dabbelt	1	-0/+4
2017-09-27	RISC-V: Paging and MMU	Palmer Dabbelt	1	-0/+282
2017-09-27	RISC-V: Device, timer, IRQs, and the SBI	Palmer Dabbelt	1	-0/+92