starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2019-12-20	riscv: move sifive_l2_cache.c to drivers/soc	Christoph Hellwig	1	-1/+0
2019-11-28	Merge tag 'ioremap-5.5' of git://git.infradead.org/users/hch/ioremap	Linus Torvalds	1	-1/+1
2019-11-18	riscv: add nommu support	Christoph Hellwig	1	-2/+1
2019-11-11	riscv: use the generic ioremap code	Christoph Hellwig	1	-1/+0
2019-09-05	riscv: move the TLB flush logic out of line	Christoph Hellwig	1	-0/+3
2019-07-04	riscv: Introduce huge page support for 32/64bit kernel	Alexandre Ghiti	1	-0/+2
2019-05-21	treewide: Add SPDX license identifier - Makefile/Kconfig	Thomas Gleixner	1	-0/+1
2019-05-17	RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs	Yash Shah	1	-0/+1
2019-05-17	riscv: move switch_mm to its own file	Gary Guo	1	-0/+1
2019-03-27	RISC-V: Always compile mm/init.c with cmodel=medany and notrace	Anup Patel	1	-0/+6
2017-11-30	RISC-V: Flush I$ when making a dirty page executable	Andrew Waterman	1	-0/+1
2017-09-27	RISC-V: Build Infrastructure	Palmer Dabbelt	1	-0/+4