starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2020-01-19	riscv: Less inefficient gcc tishift helpers (and export their symbols)	Olof Johansson	1	-18/+57
2019-12-28	riscv: fix compile failure with EXPORT_SYMBOL() & !MMU	Luc Van Oostenryck	1	-0/+4
2019-11-18	riscv: add nommu support	Christoph Hellwig	1	-6/+5
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig	1	-6/+6
2019-08-30	riscv: Using CSR numbers to access CSRs	Bin Meng	1	-6/+6
2019-08-09	RISC-V: Remove udivdi3	Palmer Dabbelt	2	-34/+0
2019-08-09	riscv: delay: use do_div() instead of __udivdi3()	Paul Walmsley	1	-1/+5
2019-06-17	Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/ke...	Linus Torvalds	1	-1/+1
2019-06-11	riscv: Fix udelay in RV32.	Nick Hu	1	-1/+1
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	5	-45/+5
2019-05-21	treewide: Add SPDX license identifier - Makefile/Kconfig	Thomas Gleixner	1	-0/+1
2018-12-21	RISC-V: lib: minor asm cleanup	Olof Johansson	2	-48/+53
2018-11-13	RISC-V: lib: Fix build error for 64-bit	Olof Johansson	1	-1/+1
2018-10-23	RISC-V: Build tishift only on 64-bit	Zong Li	1	-1/+2
2018-08-13	RISC-V: implement __lshrti3.	Alex Guo	2	-0/+43
2018-06-11	RISC-V: Make our port sparse-clean	Palmer Dabbelt	1	-2/+4
2018-06-09	riscv: split the declaration of __copy_user	Luc Van Oostenryck	1	-2/+4
2018-06-04	riscv: Fix the bug in memory access fixup code	Alan Kao	1	-4/+9
2017-11-30	RISC-V: Export some expected symbols for modules	Olof Johansson	1	-0/+1
2017-09-27	RISC-V: Build Infrastructure	Palmer Dabbelt	1	-0/+6
2017-09-27	RISC-V: Device, timer, IRQs, and the SBI	Palmer Dabbelt	1	-0/+110
2017-09-27	RISC-V: Generic library routines and assembly	Palmer Dabbelt	4	-0/+390