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path: root/arch/riscv/kernel
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2023-07-12RISC-V: Don't include Zicsr or Zifencei in I from ACPIPalmer Dabbelt1-7/+2
2023-07-07Merge tag 'riscv-for-linus-6.5-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds7-13/+17
2023-07-05risc-v: Fix order of IPI enablement vs RCU startupMarc Zyngier1-2/+3
2023-07-04RISC-V: drop error print from riscv_hartid_to_cpuid()Conor Dooley1-1/+0
2023-07-04riscv: Discard vector state on syscallsBjörn Töpel1-0/+2
2023-07-04riscv: vdso: include vdso/vsyscall.h for vdso_dataBen Dooks1-0/+1
2023-07-01riscv: vector: clear V-reg in the first-use trapAndy Chiu1-0/+1
2023-07-01riscv: vector: only enable interrupts in the first-use trapAndy Chiu1-1/+7
2023-07-01Merge patch series "riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION"Palmer Dabbelt2-9/+3
2023-06-30Merge tag 'trace-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...Linus Torvalds1-6/+1
2023-06-30Merge tag 'riscv-for-linus-6.5-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds20-130/+1363
2023-06-26Merge tag 'smp-core-2023-06-26' of ssh://gitolite.kernel.org/pub/scm/linux/ke...Linus Torvalds1-7/+7
2023-06-26riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATIONZhangjin Wu1-3/+3
2023-06-26riscv: vmlinux-xip.lds.S: remove .alternative sectionJisheng Zhang1-6/+0
2023-06-23riscv: hibernate: remove WARN_ON in save_processor_stateSong Shuai1-1/+0
2023-06-23Merge patch series "riscv: Add independent irq/softirq stacks support"Palmer Dabbelt2-2/+101
2023-06-23Merge patch series "ISA string parser cleanups"Palmer Dabbelt3-28/+116
2023-06-22riscv: stack: Support HAVE_SOFTIRQ_ON_OWN_STACKGuo Ren1-0/+35
2023-06-22riscv: stack: Support HAVE_IRQ_EXIT_ON_IRQ_STACKGuo Ren2-2/+66
2023-06-22riscv: ftrace: Enable HAVE_FUNCTION_GRAPH_RETVALDonglin Peng1-6/+1
2023-06-21RISC-V: always report presence of extensions formerly part of the base ISAConor Dooley2-0/+21
2023-06-21RISC-V: remove decrement/increment dance in ISA string parserConor Dooley1-8/+6
2023-06-21RISC-V: rework comments in ISA string parserConor Dooley1-11/+59
2023-06-21RISC-V: validate riscv,isa at boot, not during ISA string parsingConor Dooley2-9/+11
2023-06-21RISC-V: split early & late of_node to hartid mappingConor Dooley2-2/+22
2023-06-21RISC-V: simplify register width check in ISA string parsingConor Dooley1-8/+7
2023-06-20riscv: replace deprecated scall with ecallFangrui Song2-2/+2
2023-06-20riscv: uprobes: Restore thread.bad_causeTiezhu Yang1-0/+2
2023-06-20Merge patch series "RISC-V: Export Zba, Zbb to usermode via hwprobe"Palmer Dabbelt3-16/+56
2023-06-19RISC-V: hwprobe: Expose Zba, Zbb, and ZbsEvan Green1-7/+41
2023-06-19RISC-V: Track ISA extensions per hartEvan Green1-6/+12
2023-06-19RISC-V: Add Zba, Zbs extension probingEvan Green2-0/+4
2023-06-19RISC-V: ACPI : Fix for usage of pointers in different address spaceSunil V L1-2/+2
2023-06-19riscv: hibernation: Remove duplicate call of suspend_restore_csrsSong Shuai1-1/+0
2023-06-19riscv: hibernation: Replace jalr with jr before suspend_restore_regsSong Shuai1-2/+2
2023-06-14riscv: say disabling zicbom if no or bad riscv,cbom-block-size foundBen Dooks1-2/+2
2023-06-08Merge patch series "riscv: Add vector ISA support"Palmer Dabbelt12-41/+658
2023-06-08riscv: Add sysctl to set the default vector rule for new processesAndy Chiu1-1/+32
2023-06-08riscv: Add prctl controls for userspace vector managementAndy Chiu3-1/+123
2023-06-08riscv: hwcap: change ELF_HWCAP to a functionAndy Chiu1-0/+5
2023-06-08riscv: prevent stack corruption by reserving task_pt_regs(p) earlyGreentime Hu1-0/+2
2023-06-08riscv: signal: validate altstack to reflect VectorAndy Chiu1-0/+7
2023-06-08riscv: signal: Report signal frame size to userspace via auxvVincent Chen1-5/+15
2023-06-08riscv: signal: Add sigcontext save/restore for vectorGreentime Hu2-14/+163
2023-06-08riscv: signal: check fp-reserved words unconditionallyAndy Chiu1-27/+28
2023-06-08riscv: Add ptrace vector supportGreentime Hu1-0/+70
2023-06-08riscv: Allocate user's vector context in the first-use trapAndy Chiu2-2/+119
2023-06-08riscv: Add task switch support for vectorGreentime Hu1-0/+19
2023-06-08riscv: Introduce riscv_v_vsize to record size of Vector contextGreentime Hu4-0/+46
2023-06-08riscv: Disable Vector Instructions for kernel itselfGuo Ren2-9/+9